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path: root/sys/i386/pci/pci_cfgreg.c
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* number of cleanups in i386 and amd64 pci md codeavg2009-09-241-7/+7
* Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.jhb2009-05-181-0/+5
* Fall back to using configuration type 1 accesses for PCI config requests ifjhb2009-03-241-0/+2
* Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mappedjhb2008-09-111-0/+6
* Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIejhb2008-09-101-14/+44
* Extend the support for PCI-e memory mapped configuration space access:jhb2008-08-221-36/+42
* - Add support for memory mapped PCI config space access on Intel 915GMjhb2008-08-201-3/+23
* Use switch statements instead of if-else for enabling PCI-express configjhb2008-08-201-3/+9
* Integrate support for xen in to i386 common code.kmacy2008-08-151-0/+10
* MFamd64: 1.109 of pci_cfgreg.c which changes pci_cfgdisable() into a nopjhb2007-11-281-2/+6
* Adjust the code to probe for the PCI config mechanism to use.jhb2007-11-281-25/+25
* Replace a few magic numbers.jhb2006-12-121-2/+2
* Add support for 7320 and 915 PCIe chipsets.rodrigc2005-12-081-7/+11
* Provide a dummy NO_XBOX option that lives in opt_xbox.h for pc98.imp2005-11-141-2/+0
* Fix pc98 build.nyan2005-11-091-0/+2
* Add support for XBOX to the FreeBSD port. The xbox architecture isimp2005-11-091-0/+39
* MFamd64: indent with tabs instead of spaces.peter2005-11-041-1/+1
* Undo the change to pci_cfgdisable() on i386 for now. It seems to fixwpaul2005-10-251-6/+2
* Modify the pci_cfgdisable() routine to bring it more in line withwpaul2005-10-251-3/+7
* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-061-1/+1
* Remove a stray critical_exit().scottl2004-12-131-1/+0
* Expand the scope of the critical section in the PCIe read and write methodsscottl2004-12-101-4/+14
* Due to a significant addition of code, add my copyright to this file. Alsoscottl2004-12-061-0/+1
* Add support for the memory-mapped PCI Express configuration mechanism. Thisscottl2004-12-061-8/+211
* Consistently use __inline instead of __inline__ as the former is an empty macrostefanf2004-07-041-1/+1
* Trim a few things from the dmesg output and stick them under bootverbose tojhb2004-07-011-2/+2
* Switch to using the new $PIR interrupt routing code and remove the oldjhb2004-02-181-424/+5
* Replace an outb() during the test for configuration mechanism #1 with ajhb2003-12-311-1/+1
* New APIC support code:jhb2003-11-031-49/+2
* Change all SYSCTLS which are readonly and have a related TUNABLEsilby2003-10-211-1/+1
* We represent PCI intpin's two different ways. One is the way that thejhb2003-09-101-1/+1
* PC98 uses different mask of IRQ.nyan2003-08-021-2/+8
* Add hw.pci.irq_override_mask, which is a mask of interrupts that areimp2003-08-011-0/+14
* Use __FBSDID().obrien2003-06-021-3/+3
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-181-129/+28
* MFp4:imp2002-11-141-1/+1
* MFp4:imp2002-11-021-10/+34
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-021-10/+11
* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-071-7/+12
* Don't call function in return() for a void function.phk2002-09-281-3/+5
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-231-1/+4
* Axe unused include.jhb2002-09-201-1/+0
* Make sure a $PIR table header has a valid length before accepting the tablejhb2002-09-091-1/+2
* Add a function pci_probe_route_table() that returns true if our PCI BIOSjhb2002-09-061-0/+19
* Dump the $PIR table if booting verbose.jhb2002-09-061-0/+3
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validjhb2002-09-061-1/+33
* Add support for printing out the contents of a PCI BIOS $PIR interruptjhb2002-09-061-2/+54
* Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,jhb2002-09-051-2/+2
* style(9)ize the whole fileimp2002-07-211-474/+492
* Use a common function to map the bogus intlines.imp2002-06-011-11/+17
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