summaryrefslogtreecommitdiffstats
path: root/sys/i386/pci/pci_bus.c
Commit message (Expand)AuthorAgeFilesLines
* Add code to read the primary PCI bus number out of the Compaq/HP 6010jhb2005-03-251-0/+6
* /* -> /*- for copyright notices, minor format tweaks as necessaryimp2005-01-061-1/+1
* Add TUNABLE_LONG and TUNABLE_ULONG, and use the latter for thedes2004-10-311-4/+3
* Whitespace cleanupdes2004-10-311-8/+8
* Make the lower range of the memory area 0x80000000 again. Alsoimp2004-10-111-1/+15
* Add missing 'static'imp2004-10-061-2/+1
* For legacy PCI bridges, limit memory allocation to the top 32MB ofimp2004-10-061-4/+24
* Allow the pir0 device add to fail since pir0 may already exist. This shouldjhb2004-06-011-2/+2
* Add some missing <sys/module.h> includes which are masked by thephk2004-05-301-0/+1
* - Create a pir0 psuedo device as a child of legacy0 if we attach a legacyjhb2004-05-041-2/+6
* Make the legacy_pcib_attach() function static.jhb2004-05-031-1/+1
* Add back an include to fix the build for the CPU_ELAN case.jhb2004-02-191-0/+3
* Switch to using the new $PIR interrupt routing code and remove the oldjhb2004-02-181-10/+12
* Lower the priority of the legacy host to pci bridge driver so that otherjhb2003-10-311-1/+1
* - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.jhb2003-08-281-3/+3
* Prefer new location of pci include files (which have only been in theimp2003-08-221-3/+3
* The MI code was modified to filter the devices based on its headerimp2003-08-011-0/+8
* - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for ajhb2003-06-061-56/+50
* Use the secondary bus number instead of the number of the bus the PCI-PCIjhb2003-06-061-1/+5
* Use __FBSDID().obrien2003-06-021-3/+3
* Remove unused variable.phk2003-05-311-2/+1
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-181-18/+0
* Outdent the string rather than use concatenation.phk2002-12-231-2/+2
* Recognize the Serverworks CIOB30 host to pci bridge.peter2002-11-131-0/+5
* Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread().phk2002-10-201-0/+2
* "id" is never going to be -1 when it is unsigned.phk2002-10-201-2/+0
* Use the global pcib devclass instead of our own static copy.jhb2002-10-161-2/+0
* Add 2 Ids for new ServerWorks host to PCI bridge chipset.iwasaki2002-10-021-0/+8
* Now that we only probe host-PCI bridges once, we no longer have to check tojhb2002-09-231-10/+0
* Change the nexus_pcib driver (eventually to be renamed to legacy_pcib) tojhb2002-09-231-7/+7
* #include "opt_bla.h" goes first says Bruce.phk2002-09-091-2/+2
* Fix style(9) bugs.phk2002-09-081-2/+2
* Add a subclass of the PCI-PCI bridge driver that uses the PCIBIOS tojhb2002-09-061-2/+69
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validjhb2002-09-061-1/+2
* Prefer the physical bus number of the PCI bus as the unit of the pciXjhb2002-09-061-1/+1
* Change the support for AMDs ElanSC520 CPU from being a device driver tophk2002-09-041-0/+7
* Move a prototype to the least wrong place.phk2002-08-021-0/+1
* Add support for probing secondary buses on the ServerWorks Grand Championgallatin2002-07-191-0/+11
* Add initialization code for the AMD Elan sc520 which maps the MMCRphk2002-07-181-0/+2
* Add an entry for the AMD Elan SC520 hostbridge. I do not belive we canphk2002-07-181-0/+3
* Fix a PNPID in a commentimp2002-04-241-1/+1
* Major rework of the iicbus/smbus framework:nsouch2002-03-231-0/+13
* Add identification string for AMD-761 host to PCI bridge.murray2001-12-101-0/+3
* Detect a certain type of PCIBIOS brain damage. For some reason,peter2001-08-211-0/+18
* Next phase in the PCI subsystem cleanup.msmith2000-12-081-2/+2
* Hack to work around a probe which will lock up at least some i450GX-basedmsmith2000-11-081-1/+5
* Return -10000 in pci_hostb_probe to allow agp driver (disabled otherwise)ache2000-10-201-1/+1
* Add i815 Host to Hubache2000-10-201-0/+3
* Add the ability to use the $PIR table in the BIOS to route interruptsimp2000-10-161-0/+9
* Change the text for the ServerWorks north bridge chips. RCC is nowalc2000-10-141-4/+4
OpenPOWER on IntegriCloud