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* Optimize two cases in the MP locking code. First, it is not necessarydillon1999-11-191-3/+2
| | | | | | | | | | | | | | | to use a locked cmpexg when unlocking a lock that we already hold, since nobody else can touch the lock while we hold it. Second, it is not necessary to use a locked cmpexg when locking a lock that we already hold, for the same reason. These changes will allow MP locks to be used recursively without impacting performance. Modify two procedures that are called only by assembly and are already NOPROF entries to pass a critical argument in %edx instead of on the stack, removing a significant amount of code from the critical path as a consequence. Reviewed by: Alfred Perlstein <bright@wintelcom.net>, Peter Wemm <peter@netplex.com.au>
* Invoke smp_rendezvous_action() using the a.out compatible asnames.hmsmith1999-09-101-1/+1
| | | | technique (bleagh).
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
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* Modify the macros IMASK_UNLOCK, CPL_UNLOCK, and REL_FAST_INTR_LOCKalc1999-08-231-4/+2
| | | | to perform the s_unlock inline.
* Implement an all-CPU shootdown-style rendezvous facility. This allowsmsmith1999-07-201-1/+24
| | | | | | | | | | | the caller to specify a function to be guarded between an entry and exit barrier, as well as pre- and post-barrier functions. The primary use for this function is synchronised update of per-cpu private data. The implementation is almost (but not quite) MI; with a better mechanism for masking per-CPU interrupts it could probably be hoisted. Reviewed by: peter (partially)
* Go back to the old (icu.s rev.1.7 1993) way of keeping the AST-pendingbde1999-07-101-5/+4
| | | | | | | bit separate from ipending, since this is simpler and/or necessary for SMP and may even be better for UP. Reviewed by: alc, luoqi, tegge
* An SMP-specific change: Add the lock prefix to RMW operationsalc1999-07-031-1/+9
| | | | on ipending.
* Clean up bitrot in interrupt tracing code.tegge1999-06-161-3/+3
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* Unifdef VM86.jlemon1999-06-011-3/+1
| | | | Reviewed by: silence on on -current
* Fixed glitches (jumps) of about 1/HZ seconds for the i8254 timecounter.bde1999-05-281-27/+32
| | | | | | | | | | | | | | | | The old version only worked right when the time was read strictly more often than every 1/HZ seconds, but we only guarantee reading it every (1/HZ + epsilon) seconds. Part of rev.1.126-1.127 attempted to fix this but didn't succeed. Detect counter rollover using the heuristic from the old version of microtime() with additional complications for supporting calls from fast interrupt handlers. This works provided i8254 interrupts are not delayed by more than 1/(2*HZ) seconds. This needs more comments, and cleanups for the SMP case, and more testing of the SMP case before it is merged into RELENG_3. Tested by: jhay
* Enable vmspace sharing on SMP. Major changes are,luoqi1999-04-281-18/+49
| | | | | | | | | | | | | | | | | - %fs register is added to trapframe and saved/restored upon kernel entry/exit. - Per-cpu pages are no longer mapped at the same virtual address. - Each cpu now has a separate gdt selector table. A new segment selector is added to point to per-cpu pages, per-cpu global variables are now accessed through this new selector (%fs). The selectors in gdt table are rearranged for cache line optimization. - fask_vfork is now on as default for both UP and SMP. - Some aio code cleanup. Reviewed by: Alan Cox <alc@cs.rice.edu> John Dyson <dyson@iquest.net> Julian Elischer <julian@whistel.com> Bruce Evans <bde@zeta.org.au> David Greenman <dg@root.com>
* Generate intrnames[] dynamically. This should be new-bus friendly.bde1999-04-141-43/+1
| | | | Old version reviewed by: se
* Test CF after a btrl operation instead of testing ZF (which is undefined).tegge1999-04-101-2/+2
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* Maintain a mapping from irq number to (ioapic number, int pin) tuple,tegge1998-09-061-6/+11
| | | | | | | | | | | | and use this when masking/unmasking interrupts. Maintain a mapping from (iopaic number, int pin) tuple to irq number, and use this when configuring devices and programming the ioapics. Previous code assumed that irq number was equal to int pin number, and that the ioapic number was 0. Don't let an AP enter _cpu_switch before all local apics are initialized.
* Make irq forwarding truely functional.luoqi1998-09-041-11/+1
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* Register tty software interrupt handlers at run time using register_swi()bde1998-08-111-2/+2
| | | | | | | instead of at compile time using ifdefs. Use _swi_null instead of dummycamisr. CAM and dpt should call register_swi() instead of hacking on ihandlers[] directly.
* Implemented dynamic registration of software interrupt handlers. Notbde1998-08-111-10/+5
| | | | | | used yet. Use dummy SWI handlers to avoid some checks for null pointers.
* Add forwarding of roundrobin to other cpus. This gives a more regulartegge1998-05-171-3/+54
| | | | | | | | | | | update of cpu usage as shown by top when one process is cpu bound (no system calls) while the system is otherwise idle (except for top). Don't attempt to switch to the BSP in boot(). If the system was idle when an interrupt caused a panic, this won't work. Instead, switch to the BSP in cpu_reset. Remove some spurious forward_statclock/forward_hardclock warnings.
* Mask the interrupt before setting the corresponding bit in ipending iftegge1998-04-221-6/+7
| | | | | | the interrupt is already active. Don't use lock prefix for operations on ipending. Always use lock prefix for operations on iactive.
* Remove special handling for resuming clock interrupt when using APIC_IO.tegge1998-03-051-16/+1
| | | | The `generic' vector stubs do the right thing.
* When entering the apic version of slow interrupt handler, leveltegge1998-03-031-40/+303
| | | | | | | | | interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts.
* Forward the signal if the process runs on a different CPU. This reducestegge1998-03-031-5/+5
| | | | | | | | the signal handling latency for cpu-bound processes that performs very few system calls. The IPI for forcing an additional software trap is no longer dependent upon BETTER_CLOCK being defined.
* Addition of splsoftvm and a VM SWI to handle bus dma related callbacks.gibbs1998-01-151-3/+3
| | | | This SWI may be useful for other, defered, VM tasks.
* The improvements to clock statistics by Tor Eggefsmp1997-12-081-4/+146
| | | | | | | | | | | Wrappered and enabled by the define BETTER_CLOCK (on by default in smpyests.h) apic_vector.s also contains a small change I (smp) made to eliminate the double level INT problem. It seems stable, but I haven't the tools in place to prove it fixes the problem. Reviewed by: smp@csn.net Submitted by: Tor Egge <Tor.Egge@idi.ntnu.no>
* Fix a serious bug I introduced while adding in support for CAM interrupts.gibbs1997-09-281-2/+3
| | | | | | | | | | | | It seems I didn't count my 0's properly when adding the new masks into icu_vector.s pushing SWI_AST_MASK off the end of the array and screwing up the indexing for SWI_CLOCK_MASK. Fix the bug icu_vector.s and also reformat the code in both icu_vector.s and apic_vector.s so that it will be much harder to make the same mistake in the future. Submitted by: Bruce Evans <bde@zeta.org.au>
* aha1542.c aic6360.c cy.c fd.c ft.cgibbs1997-09-211-4/+7
| | | | | | | | | | | | if_ie.c if_wl.c if_zp.c isa.c isa_device.h labpc.c mcd.c ncr5380.c scd.c seagate.c si.c sio.c tw.c ultra14f.c wcd.c wd.c: Update for changes in the callout interface. apic_vector.s icu_vector.s ipl.s ipl_funcs.c: Add CAM software/hardware interrupt support.
* General cleanup of the lock pushdown code. They are grouped and enabledfsmp1997-09-071-25/+50
| | | | | | | | | from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
* Another round of lock pushdown.fsmp1997-08-301-3/+3
| | | | | | | | | Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel. UP kernel expects that this is enough to guarantee exclusive access to regions of code bracketed by these 2 functions. Add a simplelock to bracket clock accesses in clock.c: clock_lock. Help from: Bruce Evans <bde@zeta.org.au>
* Support for the new FAST_HI algorithm, enabled.fsmp1997-08-291-12/+79
| | | | | Preliminary support for the INTR_SIMPLELOCK algorithm, disabled. Note that this code is NOT ready.
* The last of the encapsolation of cpl/spl/ipending things into a criticalfsmp1997-08-241-25/+40
| | | | | | | | | | | | | | | | | | | region protected by the simplelock 'cpl_lock'. Notes: - this code is currently controlled on a section by section basis with defines in machine/param.h. All sections are currently enabled. - this code is not as clean as I would like, but that can wait till later. - the "giant lock" still surrounds most instances of this "cpl region". I still have to do the code that arbitrates setting cpl between the top and bottom halves of the kernel. - the possibility of deadlock exists, I am committing the code at this point so as to exercise it and detect any such cases B4 the "giant lock" is removed.
* Made PEND_INTS default.fsmp1997-08-211-153/+106
| | | | | | | | | | Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
* Preperation for moving cpl into critical region access.fsmp1997-08-201-8/+72
| | | | | | | | Several new fine-grained locks. New FAST_INTR() methods: - separate simplelock for FAST_INTR, no more giant lock. - FAST_INTR()s no longer checks ipending on way out of ISR. sio made MP-safe (I hope).
* Added trap specific lock calls: get_fpu_lock, etc.fsmp1997-08-101-6/+15
| | | | All resolve to the GIANT_LOCK at this time, it is purely a logical partitioning.
* Added 'lock' instruction before 3 places that update ipending.fsmp1997-08-091-1/+4
| | | | This may or may not fix the "high IO freezes SMP kernel" problem.
* Converted the TEST_LOPRIO code to default.fsmp1997-07-311-38/+5
| | | | | removed PEND_INTS 1st try direct call to MPtrylock
* Modified the PEND_INTS algorithm to fix the ISA INT loss problem.fsmp1997-07-281-2/+52
| | | | Noticed by: dave adkins <adkin003@gold.tc.umn.edu> and others.
* clock.c:fsmp1997-07-261-34/+26
| | | | | | | | | | | | | | - removed TEST_ALTTIMER. - removed APIC_PIN0_TIMER. - removed TIMER_ALL. apic_vector.s: - new algorithm where a CPU uses try_mplock instead of get_mplock: if successful continue as before. if fail set ipending bit, mask INT (to avoid recursion), cleanup & iret. This allows the CPU to return to successful work, while the ISR will be run by the CPU holding the lock as part of the doreti dance.
* New simple_lock code in asm:fsmp1997-07-231-14/+60
| | | | | | | | | | | | | | | - s_lock_init() - s_lock() - s_lock_try() - s_unlock() Created lock for IO APIC and apic_imen (SMP version of imen) - imen_lock Code to use imen_lock for access from apic_ipl.s and apic_vector.s. Moved this code *outside* of mp_lock. It seems to work!!!
* Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.fsmp1997-07-181-23/+7
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* Cleanup.fsmp1997-07-151-5/+5
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* Tighten up asm code for EOI access.fsmp1997-07-151-11/+6
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* Cleanup old stop_cpus/restart_cpus() cruft.fsmp1997-07-131-45/+37
| | | | | new code for handling mixed-mode 8259/APIC programming without 'ExtInt' new code to control other CPUs: stop_cpus()/restart_cpus()/_Xstopcpu
* First cut at code for handling "spurious INTerrupts".fsmp1997-07-061-22/+84
| | | | | | | First cut at code for handling CPU stop/restart. Notes: not working properly yet.
* apic_vector.s:fsmp1997-06-271-1/+76
| | | | | | | | | - added Xcpustop IPI code to support stop_cpus()/restart_cpus(). it is off by default, enable via smptests.h:TEST_CPUSTOP intr_machdep.h: - moved +ICULEN to lower level. - added entry for Xcpustop.
* Preliminary support for per-cpu data pages.peter1997-06-221-13/+12
| | | | | | | | | | | | | | | | This eliminates a lot of #ifdef SMP type code. Things like _curproc reside in a data page that is unique on each cpu, eliminating the expensive macros like: #define curproc (SMPcurproc[cpunumber()]) There are some unresolved bootstrap and address space sharing issues at present, but Steve is waiting on this for other work. There is still some strictly temporary code present that isn't exactly pretty. This is part of a larger change that has run into some bumps, this part is standalone so it should be safe. The temporary code goes away when the full idle cpu support is finished. Reviewed by: fsmp, dyson
* The SWI_NET_MASK and SWI_TTY_MASK handlers are now back adjacent to thepeter1997-05-311-4/+6
| | | | | | | | top of the hardware interrupt handlers. Apparently this is slightly faster with the bit scanning instruction that looks these up - this set of changes reverts the original change. Reviewed by: bde
* Split vector.s into UP and SMP specific files:fsmp1997-05-261-0/+306
- vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
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