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* Export various helper variables describing the layout and size ofjhb2015-11-121-6/+10
* The prefix for CLFLUSHOPT is 0x66. It was right on amd64.kib2015-10-301-1/+1
* Use movw instead of movl (or plain mov) when moving segment registersjhb2015-10-291-3/+3
* Add CLFLUSHOPT instruction wrappers.kib2015-10-231-0/+7
* x86/xen: Consolidate xen-os.h in a single placeroyger2015-10-211-186/+4
* xen/console: Introduce a new console driver for Xen guestroyger2015-10-081-1/+1
* Update Xen headers from 4.2 to 4.6royger2015-10-061-0/+1
* Merge stack(9) implementations for i386 and amd64 under x86/.markj2015-09-111-39/+3
* Remove unused i386 header privatespace.h. For the native kernel, itskib2015-08-071-49/+0
* Remove some more vestiges of the Xen PV domu support. Specifically,jhb2015-08-062-117/+0
* Rationalize BSD license on sys/*/include/in_cksum.hemaste2015-08-051-1/+1
* Add two new pmap functions:jah2015-08-041-1/+2
* Give large kernel stack to the initial thread . Otherwise, ZFSkib2015-08-041-0/+5
* Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUIDkib2015-08-031-0/+1
* Improve comments.kib2015-07-301-3/+3
* Use private cache line for the locked nop in *mb() on i386.kib2015-07-301-32/+39
* MFamd64 r285934: Remove store/load (= full) barrier from the i386kib2015-07-291-17/+7
* Remove duplicate and useless declarations.kib2015-07-221-1/+0
* Duplicate the copyright from the i386/i386/machdep.c intokib2015-07-101-6/+36
* Add the atomic_thread_fence() family of functions with intent tokib2015-07-081-0/+32
* Use single instance of the identical INKERNEL() and PMC_IN_KERNEL()kib2015-07-023-4/+4
* Provide npx_get_fsave(9) and npx_set_fsave(9) functions to obtain andkib2015-06-291-0/+5
* Move CS_SECURE() and EFL_SECURE() macros to the machine/frame.h. Theykib2015-06-291-0/+8
* Add a comment about too strong semantic of atomic_load_acq() on x86.kib2015-06-291-0/+9
* Reduce code duplication. Add helper fill_based_sd(9) which creates akib2015-06-291-0/+2
* Remove unneeded data dependency, currently imposed bykib2015-06-281-49/+74
* Report the values of x86 segment registers to remote debuggers.jhb2015-06-121-1/+1
* Ensure that the upper 16 bits of segment registers manually saved injhb2015-06-121-3/+6
* Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.alc2015-06-081-3/+2
* Update print_INTEL_TLB() by the tag values from the Intel SDMkib2015-06-061-0/+1
* If x86 CPU implementation of the MWAIT instruction reasonablykib2015-05-091-0/+1
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsjhb2015-04-3015-747/+11
* Move common code from sys/i386/i386/mp_machdep.c andkib2015-04-241-0/+37
* Reassign copyright statements on several files from Advancedjhb2015-04-231-1/+1
* Move some common code from sys/amd64/amd64/machdep.c andkib2015-04-221-0/+1
* Remove lazy pmap switch code from i386. Naive benchmark with md(4)kib2015-04-181-3/+1
* Add config option PAE_TABLES for the i386 kernel. It switches pmap tokib2015-04-133-14/+17
* Explain that vm_page_array is mapped to describe the memory, not thekib2015-04-081-3/+8
* Use VT-d interrupt remapping block (IR) to perform FSB messageskib2015-03-191-0/+2
* Add x2APIC support. Enable it by default if CPU is capable. Thekib2015-02-091-0/+9
* Generalized parts of the XEN timer code into a generic pvclockbryanv2015-02-041-0/+6
* loader: implement multiboot support for Xen Dom0royger2015-01-151-0/+1
* For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Pagingkib2015-01-121-0/+1
* Factor out duplicated code from dumpsys() on each architecture into genericmarkj2015-01-071-0/+6
* Revert r274772: it is not valid on MIPSemaste2014-11-251-1/+1
* Use canonical __PIC__ flagemaste2014-11-211-1/+1
* Enable the use of VM_PHYSSEG_SPARSE on amd64 and i386, making it the defaultalc2014-11-151-1/+7
* MFamd64: Add support for extended FPU states on i386. This includesjhb2014-11-024-22/+65
* MFamd64: Move extern declaration of _ucodesel and _udatasel tojhb2014-11-021-0/+2
* Remove the FP_SOFTFP flag. It wasn't used but was leftover from thejhb2014-11-021-1/+0
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