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* Major update to the way synchronization is done in the kernel. Highlightsjasone2000-09-071-4/+1
| | | | | | | | | | | | | | | include: * Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The alpha port is still in transition and currently uses both.) * Per-CPU idle processes. * Interrupts are run in their own separate kernel threads and can be preempted (i386 only). Partially contributed by: BSDi (BSD/OS) Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
* Commit major SMP cleanups and move the BGL (big giant lock) in thedillon2000-03-281-80/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
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* Remove stuff related to microtime.s, which is gone.phk1998-04-061-3/+1
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* Reenable redirection of clock interrupt to a higher priority vector.tegge1998-03-071-2/+2
| | | | | setidt() now knows about f00f_hack(), and the APs now use the same interrupt descriptor table as the BSP.
* Disable redirection of clock interrupt to a higher priority vector.tegge1998-03-041-2/+2
| | | | | This does not work on most dual Pentium machines, due to setidt() being neutralized by f00f_hack().
* When entering the apic version of slow interrupt handler, leveltegge1998-03-031-1/+32
| | | | | | | | | interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts.
* The improvements to clock statistics by Tor Eggefsmp1997-12-081-1/+22
| | | | | | | Wrappered and enabled by the define BETTER_CLOCK (on by default in smpyests.h) Reviewed by: smp@csn.net Submitted by: Tor Egge <Tor.Egge@idi.ntnu.no>
* DISABLE LEVEL_3 lock pushdown, somethings seems to have broken!fsmp1997-09-071-2/+2
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* General cleanup of the lock pushdown code. They are grouped and enabledfsmp1997-09-071-9/+109
| | | | | | | | | from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
* General cleanup of the sub-system locking macros.fsmp1997-09-011-17/+2
| | | | | | | | Eliminated the RECURSIVE_MPINTRLOCK. clock.c and microtime use clock_lock. sio.c and cy.c use com_lock. Suggestions by: Bruce Evans <bde@zeta.org.au>
* Debug version of simple_lock. This will store the CPU id of thefsmp1997-08-311-1/+15
| | | | | | | | | | holding CPU along with the lock. When a CPU fails to get the lock it compares its own id to the holder id. If they are the same it panic()s, as simple locks are binary, and this would cause a deadlock. Controlled by smptests.h: SL_DEBUG, ON by default. Some minor cleanup.
* Another round of lock pushdown.fsmp1997-08-301-1/+19
| | | | | | | | | Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel. UP kernel expects that this is enough to guarantee exclusive access to regions of code bracketed by these 2 functions. Add a simplelock to bracket clock accesses in clock.c: clock_lock. Help from: Bruce Evans <bde@zeta.org.au>
* Introduce FAST_HI option, ON by default.fsmp1997-08-291-1/+15
| | | | | This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
* Made PEND_INTS default.fsmp1997-08-211-40/+31
| | | | | | | | | | Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
* Preperation for moving cpl into critical region access.fsmp1997-08-201-17/+13
| | | | | Several new fine-grained locks. Control of new FAST_INTR() methods.
* Eliminate frequent silo overflows by restoring the TEST_LOPRIO code.fsmp1997-08-041-1/+7
| | | | | | | | This code was eliminated when the PEND_INTS algorithm was added. But it was discovered that PEND_INTS only worsen latency for FAST_INTR() routines, which can't be marked pending. Noticed & debugged by: dave adkins <adkin003@gold.tc.umn.edu>
* Converted the TEST_LOPRIO code to default.fsmp1997-07-311-11/+2
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* Comment out PEND_INTS for now, it breaks ISA INTs.fsmp1997-07-261-2/+4
| | | | Reported by: dave adkins <adkin003@gold.tc.umn.edu>
* Removed "options SMP_TIMER_NC".fsmp1997-07-261-24/+39
| | | | | | Removed TEST_ALTTIMER. Removed APIC_PIN0_TIMER. Removed TIMER_ALL.
* Developed a new strategy for handling the 8254/8259/APIC issue.fsmp1997-07-201-1/+9
| | | | Enabled (by default) with "#define NEW_STRATEGY".
* Added #define APIC_PIN0_TIMER.fsmp1997-07-191-1/+9
| | | | | | This define enables the code to ALWAYS run the 8254 timer thru the 8259 ICU. It is ON by default. It depricates the usage of "options SMP_TIMER_NC" in the config file.
* Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.fsmp1997-07-181-9/+12
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* Turned OFF DEBUG_CPUSTOP as the default. This was necessary as kernels withoutfsmp1997-07-171-2/+2
| | | | DDB failed to link for lack of db_printf().
* Cleanup.fsmp1997-07-151-50/+56
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* New defines to eliminate "magic numbers" in various places.fsmp1997-07-151-3/+11
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* Many new test defines, including:fsmp1997-07-131-6/+88
| | | | | | | | - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
* Additional debugging functions and macros.fsmp1997-07-061-2/+37
| | | | "spurious INTerrupt" support.
* Preliminaries for stop_cpus()/restart_cpus().fsmp1997-06-271-3/+8
| | | | | | Both are turned off by default. Added macro for displaying POST codes from kernel.
* Added a test called 'LATE_START'.fsmp1997-05-261-1/+6
| | | | | | | | | This is now the default, it delays most of the MP startup to the function machdep.c:cpu_startup(). It should be possible to move the 2 functions found there (mp_start() & mp_announce()) even further down the path once we know exactly where that should be... Help from: Peter Wemm <peter@spinner.dialix.com.au>
* removed TEST_CPUHITS code.fsmp1997-04-281-10/+1
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* removed all the TEST_UPPERPRIO crud.fsmp1997-04-281-10/+1
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* informal discussion between Bruce Evans <bde@zeta.org.au>,fsmp1997-04-271-15/+1
| | | | | | | Peter Wemm <peter@spinner.DIALix.COM>, Steve Passe <smp@csn.net> removed all the IPI_INTS code. made the XFAST_IPI32 code default, renaming Xfastipi32 to Xinvltlb.
* Man the liferafts! Here comes the long awaited SMP -> -current merge!peter1997-04-261-0/+92
There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
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