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* MFC 305836: Remove 'cpu' and 'cpu_class' on amd64.jhb2016-11-081-0/+1
| | | | | | | | The 'cpu' and 'cpu_class' variables were always set to the same value on amd64 and are legacy holdovers from i386. Remove them entirely on amd64. Requested by: kib (MFC)
* Type of the interrupt handlers on x86 cannot be expressed in C.kib2016-03-291-1/+0
| | | | | | | | Simplify and unify placeholder type definitions. Reviewed by: jhb Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D5771
* Merge common parts of i386 and amd64 md_var.h and smp.h intokib2015-12-071-65/+2
| | | | | | | | new headers x86/include x86_var.h and x86_smp.h. Reviewed by: emaste, jhb Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D4358
* Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUIDkib2015-08-031-0/+1
| | | | | | | | | | | | | | reported, on APs. We already did this on BSP. Otherwise, the userspace software which depends on the features reported by the high CPUID levels is misbehaving. In particular, AVX detection is non-functional, depending on which CPU thread happens to execute when doing CPUID. Another victim is the libthr signal handlers interposer, which needs to save full FPU extended state. Reported and tested by: Andre Meiser <ortadur@web.de> Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Reduce code duplication. Add helper fill_based_sd(9) which creates akib2015-06-291-0/+2
| | | | | | | based user data descriptor covering whole VA. Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Update print_INTEL_TLB() by the tag values from the Intel SDMkib2015-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | rev. 55. The modern CPUs cache and TLB descriptions looked quite questionable without the update, e.g. Haswell i7 4770S reported: Data TLB: 4 KB pages, 4-way set associative, 64 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line After the update, the report is: Data TLB: 1 GByte pages, 4-way set associative, 4 entries Data TLB: 4 KB pages, 4-way set associative, 64 entries Instruction TLB: 2M/4M pages, fully associative, 8 entries Instruction TLB: 4KByte pages, 8-way set associative, 64 entries 64-Byte prefetching Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line Some tags were apparently removed from the table 3-21, Vol. 2A. Keep them around, but add a comment stating the removal. Update the format line for cpu_stdext_feature according to the bits from the SDM rev.55. It appears that Haswells do not store %cs and %ds values in the FPU save area. Store content of the %ecx register from the CPUID leaf 0x7 subleaf 0 as cpu_stdext_feature2 and print defined bits from it, again acording to SDM rev. 55. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* If x86 CPU implementation of the MWAIT instruction reasonablykib2015-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | interacts with interrupts, query ACPI and use MWAIT for entrance into Cx sleep states. Support C1 "I/O then halt" mode. See Intel' document 302223-007 "Intelб╝ Processor Vendor-Specific ACPI Interface Specification" for description. Move the acpi_cpu_c1() function into x86/cpu_machdep.c and use it instead of inlining "sti; hlt" sequence in several places. In the acpi(4) man page, besides documenting the dev.cpu.N.cx_methods sysctl, correct the names for dev.cpu.N.{cx_usage,cx_lowest,cx_supported} sysctls. Both jkim and avg have some other patches implementing the mwait functionality; this work is unrelated. Linux does not rely on the ACPI to provide correct tables describing Cx modes. Instead, the driver has pre-defined knowledge of the CPU models, it was supplied by Intel. Tested by: pho (previous versions) Sponsored by: The FreeBSD Foundation
* Move some common code from sys/amd64/amd64/machdep.c andkib2015-04-221-0/+1
| | | | | | | | sys/i386/i386/machdep.c to new file sys/x86/x86/cpu_machdep.c. Most of the code is related to the idle handling. Discussed with: pluknet Sponsored by: The FreeBSD Foundation
* For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Pagingkib2015-01-121-0/+1
| | | | | | | | | Features by CPUID as CPUID.80000008H:EAX[7:0], into variable cpu_maxphyaddr. Reviewed by: alc Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 1 week
* MFamd64: Add support for extended FPU states on i386. This includesjhb2014-11-021-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | support for AVX on i386. - Similar to amd64, move the FPU save area out of the PCB and instead store saved FPU state in a variable-sized buffer after the PCB on the stack. - To support the variable PCB location, alter the locore code to only use the bottom-most page of proc0stack for init386(). init386() returns the correct stack pointer to locore which adjusts the stack for thread0 before calling mi_startup(). - Don't bother setting cr3 in thread0's pcb in locore before calling init386(). It wasn't used (init386() overwrote it at the end) and it doesn't work with the variable-sized FPU save area. - Remove the new-bus attachment from npx. This was only ever useful for external co-processors using IRQ13, but those have not been supported for several years. npxinit() is now called much earlier during boot (init386()) similar to amd64. - Implement PT_{GET,SET}XSTATE and I386_GET_XFPUSTATE. - npxsave() is now only called from context switch contexts so it can use XSAVEOPT. Differential Revision: https://reviews.freebsd.org/D1058 Reviewed by: kib Tested on: FreeBSD/i386 VM under bhyve on Intel i5-2520
* MFamd64: Move extern declaration of _ucodesel and _udatasel tojhb2014-11-021-0/+2
| | | | <machine/md_var.h>
* Rework virtual machine hypervisor detection.jhb2014-10-281-0/+2
| | | | | | | | | | | | | | | - Move the existing code to x86/x86/identcpu.c since it is x86-specific. - If the CPUID2_HV flag is set, assume a hypervisor is present and query the 0x40000000 leaf to determine the hypervisor vendor ID. Export the vendor ID and the highest supported hypervisor CPUID leaf via hv_vendor[] and hv_high variables, respectively. The hv_vendor[] array is also exported via the hw.hv_vendor sysctl. - Merge the VMWare detection code from tsc.c into the new probe in identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in the TSC code to identify VMWare. Differential Revision: https://reviews.freebsd.org/D1010 Reviewed by: delphij, jkim, neel
* Pass up the error status of minidumpsys() to its callers.markj2014-10-081-1/+1
| | | | | | PR: 193761 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Sponsored by: EMC / Isilon Storage Division
* MFamd64: Use initializecpu() to set various model-specific registers onjhb2014-09-101-1/+1
| | | | | | | | | | | | | | AP startup and AP resume (it was already used for BSP startup and BSP resume). - Split code to do one-time probing of cache properties out of initializecpu() and into initializecpucache(). This is called once on the BSP during boot. - Move enable_sse() into initializecpu(). - Call initializecpu() for AP startup instead of enable_sse() and manually frobbing MSR_EFER to enable PG_NX. - Call initializecpu() when an AP resumes. In theory this will now properly re-enable PG_NX in MSR_EFER when resuming a PAE kernel on APs.
* To workaround an errata on certain Pentium Pro CPUs, i386 disablesjhb2014-09-101-0/+1
| | | | | | | the local APIC in initializecpu() and re-enables it if the APIC code decides to use the local APIC after all. Rework this workaround slightly so that initializecpu() won't re-disable the local APIC if it is called after the APIC code re-enables the local APIC.
* Move code to set various MSRs on AMD cpus out of printcpuinfo() andjhb2014-09-101-5/+0
| | | | into initalizecpu() instead.
* Merge the amd64 and i386 identcpu.c into a single x86 implementation.jhb2014-09-041-0/+1
| | | | | This brings the structured extended features mask and VT-x reporting to i386 and Intel cache and TLB info (under bootverbose) to amd64.
* - Move prototypes for various functions into out of C files and intojhb2014-09-041-2/+13
| | | | | | | | | | <machine/md_var.h>. - Move some CPU-related variables out of i386/i386/identcpu.c to initcpu.c to match amd64. - Move the declaration of has_f00f_hack out of identcpu.c to machdep.c. - Remove a misleading comment from i386/i386/initcpu.c (locore zeros the BSS before it calls identify_cpu()) and remove explicit zero assignments to reduce the diff with amd64.
* x86: detect mwait capabilities and extensions, when presentavg2013-07-281-0/+3
| | | | | Reviewed by: kib (earlier amd64-only version) MFC after: 2 weeks
* Add SMP/i386 suspend/resume support.iwasaki2012-05-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most part is merged from amd64. - i386/acpica/acpi_wakecode.S Replaced with amd64 code (from realmode to paging enabling code). - i386/acpica/acpi_wakeup.c Replaced with amd64 code (except for wakeup_pagetables stuff). - i386/include/pcb.h - i386/i386/genassym.c Added PCB new members (CR0, CR2, CR4, DS, ED, FS, SS, GDT, IDT, LDT and TR) needed for suspend/resume, not for context switch. - i386/i386/swtch.s Added suspendctx() and resumectx(). Note that savectx() was not changed and used for suspending (while amd64 code uses it). BSP and AP execute the same sequence, suspendctx(), acpi_wakecode() and resumectx() for suspend/resume (in case of UP system also). - i386/i386/apic_vector.s Added cpususpend(). - i386/i386/mp_machdep.c - i386/include/smp.h Added cpususpend_handler(). - i386/include/apicvar.h - kern/subr_smp.c - sys/smp.h Added IPI_SUSPEND and suspend_cpus(). - i386/i386/initcpu.c - i386/i386/machdep.c - i386/include/md_var.h - pc98/pc98/machdep.c Moved initializecpu() declarations to md_var.h. MFC after: 3 days
* Remove unused i586 optimized bcopy/bzero/etc implementations that utilizekib2010-06-231-10/+0
| | | | | | | | | FPU registers for copying. Remove the switch table and jumps from bcopy/bzero/... to the actual implementation. As a side-effect, i486-optimized bzero is removed. Reviewed by: bde Tested by: pho (previous version)
* Adapt r204907 and r205402, the amd64 implementation of the workaround foralc2010-03-241-0/+1
| | | | | | | | | | | AMD Family 10h Erratum 383, to i386. Enable machine check exceptions by default, just like r204913 for amd64. Enable superpage promotion only if the processor actually supports large pages, i.e., PG_PS. MFC after: 2 weeks
* As was done in r195820 for amd64, use clflush for flushing cache lineskib2009-07-291-0/+1
| | | | | | | | | | | | when memory page caching attributes changed, and CPU does not support self-snoop, but implemented clflush, for i386. Take care of possible mappings of the page by sf buffer by utilizing the mapping for clflush, otherwise map the page transiently. Amd64 used direct map. Proposed and reviewed by: alc Approved by: re (kensmith)
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-0/+1
| | | | Reviewed by: jhb, peter (early amd64 version)
* Detect Advanced Power Management Information for AMD CPUs.jkim2008-10-211-0/+1
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* Initialise (if necessary) the VIA C3/C7 features.mr2006-07-121-0/+2
| | | | | | | Store the capabilities for further use by random(4), padlock(4), ... Obtained from: mostly OpenBSD MFC after: 1 week
* Use the method described in IA-32 Intel Architecture Software Developer'sdavidxu2006-05-301-0/+1
| | | | | | | Manual chapter 11.6.6 to get valid mxcsr bits, use the mxcsr mask to clear invalid bits passed by user code. Reviewed by: bde
* Merge minidumps from amd64 where they were originally developed.peter2006-04-211-0/+6
| | | | | | | | | | | | | Major differences: * since there is no direct map region, there is no custom uma memory allocator to modify to include its pages in the dumps. * Various data entries are reduced from 64 bit to 32 bit to match the native size. dump_add_page() and dump_drop_page() are still present in case one wants to arrange for arbitary pages to be dumped. This is of marginal use though because libkvm+kgdb cannot address physical memory that isn't mapped into kvm.
* - Print number of physical/logical cores and more CPUID info.jkim2005-10-141-0/+2
| | | | | | | | | - Add newer CPUID definitions for future use. Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2. Approved by: anholt (mentor)
* Begin promoting the AMD-originated feature flags to first class flags, nowpeter2005-06-301-1/+3
| | | | | | | | | | | | | | | | | that newer Intel cpu hardware implements them too. This includes things like the NX (pte no-execute) flag for execute protection. We'll need to reference this for implementing no-exec in pmap.c at some point. Some feature flags are duplicated in both the Intel-orignated bits and the AMD bits. Suppress the the duplicates correctly - the old code assumed they were a 1:1 mapping which is not correct. We can't just mask off the bits present in cpu_feature. Converge with amd64 where this originated from. Intel cpu's that implement any AMD features will report them in dmesg now. Approved by: re
* Add the 2nd word of IA32 feature flags. This includes things such as SSE3.obrien2005-05-161-1/+1
| | | | Obtained from: sys/amd64/amd64/identcpu.
* Move pc98 specific parts to the pc98 specific file.imp2005-04-031-4/+0
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* Remove atdevbase and replace it's remaining uses with direct references tojhb2004-06-101-1/+0
| | | | KERNBASE instead.
* - is_physical_memory()'s parameter, which is a physical address, should bealc2004-04-111-1/+1
| | | | a vm_paddr_t not a vm_offset_t.
* Add struct definition of the Elan MMCR registers (from jb@)phk2004-01-051-1/+0
| | | | | | | | Put a CTASSERT() on the size of the struct. Use the struct where it is easy to do so in elan_mmcr.c Add the Elan specific hardware reset code (also from jb@).
* Catch up to interrupt code changes.jhb2003-11-031-0/+2
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* - Add ss2_pagezero() for zeroing pages using the movnti instruction. Thisjeff2003-10-011-0/+1
| | | | | instruction is enabled with SSE2 but does not use SSE registers. It is a "non-temporal" move which bypasses the cache and does not dirty lines.
* Further cleanup <machine/cpu.h> and <machine/md_var.h>: move the MImarcel2003-08-161-3/+0
| | | | | | | | | | | | | | | | | | | prototypes of cpu_halt(), cpu_reset() and swi_vm() from md_var.h to cpu.h. This affects db_command.c and kern_shutdown.c. ia64: move all MD prototypes from cpu.h to md_var.h. This affects madt.c, interrupt.c and mp_machdep.c. Remove is_physical_memory(). It's not used (vm_machdep.c). alpha: the MD prototypes have been left in cpu.h with a comment that they should be there. Moving them is left for later. It was expected that the impact would be significant enough to be done in a seperate commit. powerpc: MD prototypes left in cpu.h. Comment added. Suggested by: bde Tested with: make universe (pc98 incomplete)
* Tidy up leftover lazy_switch instrumentation that is no longer needed.peter2003-06-271-16/+0
| | | | This cleans up some #ifdef hell.
* Define ovbcopy() as a macro which expands to the equivalent bcopy() call,des2003-04-041-4/+5
| | | | | | | | | | | | | | to take care of the KAME IPv6 code which needs ovbcopy() because NetBSD's bcopy() doesn't handle overlap like ours. Remove all implementations of ovbcopy(). Previously, bzero was a function pointer on i386, to save a jmp to bzero_vector. Get rid of this microoptimization as it only confuses things, adds machine-dependent code to an MD header, and doesn't really save all that much. This commit does not add my pagezero() / pagecopy() code.
* Commit a partial lazy thread switch mechanism for i386. it isn't as lazypeter2003-04-021-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as it could be and can do with some more cleanup. Currently its under options LAZY_SWITCH. What this does is avoid %cr3 reloads for short context switches that do not involve another user process. ie: we can take an interrupt, switch to a kthread and return to the user without explicitly flushing the tlb. However, this isn't as exciting as it could be, the interrupt overhead is still high and too much blocks on Giant still. There are some debug sysctls, for stats and for an on/off switch. The main problem with doing this has been "what if the process that you're running on exits while we're borrowing its address space?" - in this case we use an IPI to give it a kick when we're about to reclaim the pmap. Its not compiled in unless you add the LAZY_SWITCH option. I want to fix a few more things and get some more feedback before turning it on by default. This is NOT a replacement for Bosko's lazy interrupt stuff. This was more meant for the kthread case, while his was for interrupts. Mine helps a little for interrupts, but his helps a lot more. The stats are enabled with options SWTCH_OPTIM_STATS - this has been a pseudo-option for years, I just added a bunch of stuff to it. One non-trivial change was to select a new thread before calling cpu_switch() in the first place. This allows us to catch the silly case of doing a cpu_switch() to the current process. This happens uncomfortably often. This simplifies a bit of the asm code in cpu_switch (no longer have to call choosethread() in the middle). This has been implemented on i386 and (thanks to jake) sparc64. The others will come soon. This is actually seperate to the lazy switch stuff. Glanced at by: jake, jhb
* - Add vm_paddr_t, a physical address type. This is required for systemsjake2003-03-251-1/+1
| | | | | | | | | | | | | | | where physical addresses larger than virtual addresses, such as i386s with PAE. - Use this to represent physical addresses in the MI vm system and in the i386 pmap code. This also changes the paddr parameter to d_mmap_t. - Fix printf formats to handle physical addresses >4G in the i386 memory detection code, and due to kvtop returning vm_paddr_t instead of u_long. Note that this is a name change only; vm_paddr_t is still the same as vm_offset_t on all currently supported platforms. Sponsored by: DARPA, Network Associates Laboratories Discussed with: re, phk (cdevsw change)
* - Move enable_sse()'s prototype to machine/md_var.h.jhb2003-01-221-2/+3
| | | | | | | | - Sort definition of cpu_* variables appropriately. - Move cpu_fxsr out of the magic non-BSS set of variables and stick it in the BSS along with hw_instruction_sse (make the latter static as well). Submitted by: bde (partially)
* Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename thisjhb2003-01-221-1/+1
| | | | | | | variable to something in the cpu_* namespace since that's what all the other cpuid variables were named and cpu_procinfo is what I came up with. Requested by: bde
* Rework part of the previous processor name changes so that we readjhb2003-01-091-1/+0
| | | | | | | | cpu_exthigh and cpu_brand in printcpuinfo() instead of in identify_cpu(). We also only do it for known-good values of cpu_vendor which is a bit more conservative. Reviewed by: bde (mostly)
* - Add a cpu_exthigh variable to hold the highest extended cpuid valuejhb2003-01-081-0/+2
| | | | | | | | | returned from cpuid 0x80000000. - Add a cpu_brand char array to hold the processor name returned by cpuid 0x80000002-0x80000004 on AMD, Intel, Transmeta, and possibly other CPUs. - Use cpuid to set cpu_exthigh and read the processor name if it is present in identify_cpu().
* Add a cpuid_cpuinfo variable to hold the results of %ebx from cpuid withjhb2003-01-081-0/+1
| | | | %eax of 1 and set it in identify_cpu().
* Split 4.x and 5.x signal handling so that we can keep 4.x signalpeter2002-10-251-1/+7
| | | | | | | | | | | | | | | | handling clean and functional as 5.x evolves. This allows some of the nasty bandaids in the 5.x codepaths to be unwound. Encapsulate 4.x signal handling under COMPAT_FREEBSD4 (there is an anti-foot-shooting measure in place, 5.x folks need this for a while) and finish encapsulating the older stuff under COMPAT_43. Since the ancient stuff is required on alpha (longjmp(3) passes a 'struct osigcontext *' to the current sigreturn(2), instead of the 'ucontext_t *' that sigreturn is supposed to take), add a compile time check to prevent foot shooting there too. Add uniform COMPAT_43 stubs for ia64/sparc64/powerpc. Tested on: i386, alpha, ia64. Compiled on sparc64 (a few days ago). Approved by: re
* Change hw.physmem and hw.usermem to unsigned long like they used to bepeter2002-08-301-1/+1
| | | | | | | | | | | | | in the original hardwired sysctl implementation. The buf size calculator still overflows an integer on machines with large KVA (eg: ia64) where the number of pages does not fit into an int. Use 'long' there. Change Maxmem and physmem and related variables to 'long', mostly for completeness. Machines are not likely to overflow 'int' pages in the near term, but then again, 640K ought to be enough for anybody. This comes for free on 32 bit machines, so why not?
* Move a prototype to the least wrong place.phk2002-08-021-0/+1
| | | | Suggested by: bde
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