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* MFC r312555:kib2017-02-031-0/+7
| | | | Use SFENCE for ordering CLFLUSHOPT.
* The prefix for CLFLUSHOPT is 0x66. It was right on amd64.kib2015-10-301-1/+1
| | | | Sponsored by: The FreeBSD Foundation
* Add CLFLUSHOPT instruction wrappers.kib2015-10-231-0/+7
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsjhb2015-04-301-42/+4
| | | | | | | | | | | | | | | | | | | | | remains. Xen is planning to phase out support for PV upstream since it is harder to maintain and has more overhead. Modern x86 CPUs include virtualization extensions that support HVM guests instead of PV guests. In addition, the PV code was i386 only and not as well maintained recently as the HVM code. - Remove the i386-only NATIVE option that was used to disable certain components for PV kernels. These components are now standard as they are on amd64. - Remove !XENHVM bits from PV drivers. - Remove various shims required for XEN (e.g. PT_UPDATES_FLUSH, LOAD_CR3, etc.) - Remove duplicate copy of <xen/features.h>. - Remove unused, i386-only xenstored.h. Differential Revision: https://reviews.freebsd.org/D2362 Reviewed by: royger Tested by: royger (i386/amd64 HVM domU and amd64 PVH dom0) Relnotes: yes
* Add x2APIC support. Enable it by default if CPU is capable. Thekib2015-02-091-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | hw.x2apic_enable tunable allows disabling it from the loader prompt. To closely repeat effects of the uncached memory ops when accessing registers in the xAPIC mode, the x2APIC writes to MSRs are preceeded by mfence, except for the EOI notifications. This is probably too strict, only ICR writes to send IPI require serialization to ensure that other CPUs see the previous actions when IPI is delivered. This may be changed later. In vmm justreturn IPI handler, call doreti_iret instead of doing iretd inline, to handle corner conditions. Note that the patch only switches LAPICs into x2APIC mode. It does not enables FreeBSD to support > 255 CPUs, which requires parsing x2APIC MADT entries and doing interrupts remapping, but is the required step on the way. Reviewed by: neel Tested by: pho (real hardware), neel (on bhyve) Discussed with: jhb, grehan Sponsored by: The FreeBSD Foundation MFC after: 2 months
* MFamd64: Add support for extended FPU states on i386. This includesjhb2014-11-021-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | support for AVX on i386. - Similar to amd64, move the FPU save area out of the PCB and instead store saved FPU state in a variable-sized buffer after the PCB on the stack. - To support the variable PCB location, alter the locore code to only use the bottom-most page of proc0stack for init386(). init386() returns the correct stack pointer to locore which adjusts the stack for thread0 before calling mi_startup(). - Don't bother setting cr3 in thread0's pcb in locore before calling init386(). It wasn't used (init386() overwrote it at the end) and it doesn't work with the variable-sized FPU save area. - Remove the new-bus attachment from npx. This was only ever useful for external co-processors using IRQ13, but those have not been supported for several years. npxinit() is now called much earlier during boot (init386()) similar to amd64. - Implement PT_{GET,SET}XSTATE and I386_GET_XFPUSTATE. - npxsave() is now only called from context switch contexts so it can use XSAVEOPT. Differential Revision: https://reviews.freebsd.org/D1058 Reviewed by: kib Tested on: FreeBSD/i386 VM under bhyve on Intel i5-2520
* provide fast versions of ffsl and flsl for i386; ffsll and flsll for amd64avg2014-02-141-0/+16
| | | | | | | Reviewed by: jhb MFC after: 10 days X-MFC note: consider thirdparty modules depending on these symbols Sponsored by: HybridCluster
* Add lfence().kib2012-08-011-0/+7
| | | | MFC after: 1 week
* Add a clts() wrapper around the 'clts' instruction to <machine/cpufunc.h>jhb2012-07-091-0/+10
| | | | | | | | | | | on x86 and use that to implement stop_emulating() in the fpu/npx code. Reimplement start_emulating() in the non-XEN case by using load_cr0() and rcr0() instead of the 'lmsw' and 'smsw' instructions. Intel explicitly discourages the use of 'lmsw' and 'smsw' on 80386 and later processors in the description of these instructions in Volume 2 of the ADM. Reviewed by: kib MFC after: 1 month
* Correct cpu_monitor() and cpu_mwait() for amd64. These instructions takejkim2011-07-051-5/+7
| | | | | | %rcx as "extensions" in long mode. If any unused bit is set in %rcx, these instructions cause general protection fault. Fix style nits and synchronize i386 with amd64.
* Add a function rdtsc32() to read lower 32 bits from TSC and discard upperjkim2011-04-141-0/+9
| | | | | | 32 bits. Some times compiler inserts unnecessary instructions to preserve unused upper 32 bits even when it is casted to a 32-bit value. It reduces such compiler mistakes where every cycle counts.
* Consistently use __volatile as the rest of this file.jkim2011-04-141-5/+5
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* Consistently use C99 standard integers as the rest of this file.jkim2011-04-141-6/+6
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* Change the parameter passed to the inline assembly to u_shortrdivacky2010-09-031-15/+15
| | | | | | | | as we are dealing with 16bit segment registers. Change mov to movw. Approved by: rpaulo (mentor) Reviewed by: kib, rink
* Quiet variable "shadows" warning:obrien2010-01-011-18/+18
| | | | | | | sys/vmmeter.h: warning: shadowed declaration is here machine/cpufunc.h: In function 'insw': machine/cpufunc.h: warning: declaration of 'cnt' shadows a global declaration ..snip..
* make read_eflags and write_eflags accomplish the same effect on PVM as native,kmacy2009-10-011-10/+10
| | | | simplifying interrupt handling
* cpufunc.h: unify/correct style of c extension namesavg2009-09-301-2/+2
| | | | | | | | | | i386 and amd64 archs only. inline => __inline. [1] __asm__ => __asm. [2] Reviewed by: kib, jhb [1] Suggested by: kib [2] MFC after: 1 week
* As was done in r195820 for amd64, use clflush for flushing cache lineskib2009-07-291-0/+14
| | | | | | | | | | | | when memory page caching attributes changed, and CPU does not support self-snoop, but implemented clflush, for i386. Take care of possible mappings of the page by sf buffer by utilizing the mapping for clflush, otherwise map the page transiently. Amd64 used direct map. Proposed and reviewed by: alc Approved by: re (kensmith)
* Move (read|write)_cyrix_reg() inlines from specialreg.h to cpufunc.h.jhb2009-06-161-0/+16
| | | | specialreg.h now consists solely of register-related macros.
* Clobber "cc" instead of using volatile.ed2009-06-131-2/+2
| | | | Submitted by: Christoph Mallon
* Simplify in/out functions (for i386 and AMD64).ed2009-04-111-79/+8
| | | | | | | | Remove a hack to generate more efficient code for port numbers below 0x100, which has been obsolete for at least ten years, because GCC has an asm constraint to specify that. Submitted by: Christoph Mallon <christoph mallon gmx de>
* Change some movl's to mov's. Newer GAS no longer accept 'movl' instructionsobrien2009-01-311-5/+5
| | | | | | for moving between a segment register and a 32-bit memory location. Looked at by: jhb
* - move gdt, ldt allocation to before KPT allocationkmacy2008-10-191-2/+6
| | | | | | | | | - fix bugs where we would: - try to map the hypervisors address space - accidentally kick out an existing kernel mapping for some domain creation memory allocation sizes - accidentally skip a 2MB kernel mapping for some domain creation memory allocation sizes - don't rely on trapping in to xen to read rcr2, reference through vcpu - whitespace cleanups
* - clean up interrupt handling for xen a tiny bitkmacy2008-08-201-3/+3
| | | | | | | - parse the command line in to kenv - defer shutdown watcher until later in boot MFC after: 1 month
* Integrate support for xen in to i386 common code.kmacy2008-08-151-4/+40
| | | | MFC after: 1 month
* - Add cpuctl(4) pseudo-device driver to provide access to some low-levelstas2008-08-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpucontrol(8) utility, that provides userland access to the features of cpuctl(4). - Add subsequent manpages. The cpuctl(4) device operates as follows. The pseudo-device node cpuctlX is created for each cpu present in the systems. The pseudo-device minor number corresponds to the cpu number in the system. The cpuctl(4) pseudo- device allows a number of ioctl to be preformed, namely RDMSR/WRMSR/CPUID and UPDATE. The first pair alows the caller to read/write machine-specific registers from the correspondent CPU. cpuid data could be retrieved using the CPUID call, and microcode updates are applied via UPDATE. The permissions are inforced based on the pseudo-device file permissions. RDMSR/CPUID will be allowed when the caller has read access to the device node, while WRMSR/UPDATE will be granted only when the node is opened for writing. There're also a number of priv(9) checks. The cpucontrol(8) utility is intened to provide userland access to the cpuctl(4) device features. The utility also allows one to apply cpu microcode updates. Currently only Intel and AMD cpus are supported and were tested. Approved by: kib Reviewed by: rpaulo, cokane, Peter Jeremy MFC after: 1 month
* - Add inlines for the monitor and mwait instructions.jeff2008-04-181-0/+13
| | | | Sponsored by: Nokia
* Add "show sysregs" command to ddb. On i386, this gives gdt, idt, ldt,njl2007-08-091-11/+47
| | | | | | | | cr0-4, etc. Support should be added for other platforms that have a different set of registers for system use. Loosely based on: OpenBSD Approved by: re
* Add a knob for disabling/enabling HTT, "machdep.hyperthreading_allowed".nectar2005-05-131-0/+8
| | | | | | | Default off due to information disclosure on multi-user systems. Submitted by: cperciva Reviewed by: jhb
* netchild's mega-patch to isolate compiler dependencies into a centraljoerg2005-03-021-6/+10
| | | | | | | | | | | | | | | | place. This moves the dependency on GCC's and other compiler's features into the central sys/cdefs.h file, while the individual source files can then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42. By now, GCC and ICC (the Intel compiler) have been actively tested on IA32 platforms by netchild. Extension to other compilers is supposed to be possible, of course. Submitted by: netchild Reviewed by: various developers on arch@, some time ago
* Remove advertising clause from University of California Regent'simp2004-04-071-4/+0
| | | | | | | license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson. Approved by: core, peter, alc, rwatson
* Move the definition of rss() from db_interface.c to cpufunc.h wheremarcel2004-04-031-0/+8
| | | | | | it belongs. Change the implementation to match those of rfs() and rgs() for consistency and irrespective of whether the original was more correct or not (technically speaking).
* These are changes to allow to use the Intel C/C++ compiler (lang/icc)trhodes2004-03-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to build the kernel. It doesn't affect the operation if gcc. Most of the changes are just adding __INTEL_COMPILER to #ifdef's, as icc v8 may define __GNUC__ some parts may look strange but are necessary. Additional changes: - in_cksum.[ch]: * use a generic C version instead of the assembly version in the !gcc case (ASM code breaks with the optimizations icc does) -> no bad checksums with an icc compiled kernel Help from: andre, grehan, das Stolen from: alpha version via ppc version The entire checksum code should IMHO be replaced with the DragonFly version (because it isn't guaranteed future revisions of gcc will include similar optimizations) as in: ---snip--- Revision Changes Path 1.12 +1 -0 src/sys/conf/files.i386 1.4 +142 -558 src/sys/i386/i386/in_cksum.c 1.5 +33 -69 src/sys/i386/include/in_cksum.h 1.5 +2 -0 src/sys/netinet/igmp.c 1.6 +0 -1 src/sys/netinet/in.h 1.6 +2 -0 src/sys/netinet/ip_icmp.c 1.4 +3 -4 src/contrib/ipfilter/ip_compat.h 1.3 +1 -2 src/sbin/natd/icmp.c 1.4 +0 -1 src/sbin/natd/natd.c 1.48 +1 -0 src/sys/conf/files 1.2 +0 -1 src/sys/conf/files.amd64 1.13 +0 -1 src/sys/conf/files.i386 1.5 +0 -1 src/sys/conf/files.pc98 1.7 +1 -1 src/sys/contrib/ipfilter/netinet/fil.c 1.10 +2 -3 src/sys/contrib/ipfilter/netinet/ip_compat.h 1.10 +1 -1 src/sys/contrib/ipfilter/netinet/ip_fil.c 1.7 +1 -1 src/sys/dev/netif/txp/if_txp.c 1.7 +1 -1 src/sys/net/ip_mroute/ip_mroute.c 1.7 +1 -2 src/sys/net/ipfw/ip_fw2.c 1.6 +1 -2 src/sys/netinet/igmp.c 1.4 +158 -116 src/sys/netinet/in_cksum.c 1.6 +1 -1 src/sys/netinet/ip_gre.c 1.7 +1 -2 src/sys/netinet/ip_icmp.c 1.10 +1 -1 src/sys/netinet/ip_input.c 1.10 +1 -2 src/sys/netinet/ip_output.c 1.13 +1 -2 src/sys/netinet/tcp_input.c 1.9 +1 -2 src/sys/netinet/tcp_output.c 1.10 +1 -1 src/sys/netinet/tcp_subr.c 1.10 +1 -1 src/sys/netinet/tcp_syncache.c 1.9 +1 -2 src/sys/netinet/udp_usrreq.c 1.5 +1 -2 src/sys/netinet6/ipsec.c 1.5 +1 -2 src/sys/netproto/ipsec/ipsec.c 1.5 +1 -1 src/sys/netproto/ipsec/ipsec_input.c 1.4 +1 -2 src/sys/netproto/ipsec/ipsec_output.c and finally remove sys/i386/i386 in_cksum.c sys/i386/include in_cksum.h ---snip--- - endian.h: * DTRT in C++ mode - quad.h: * we don't use gcc v1 anymore, remove support for it Suggested by: bde (long ago) - assym.h: * avoid zero-length arrays (remove dependency on a gcc specific feature) This change changes the contents of the object file, but as it's only used to generate some values for a header, and the generator knows how to handle this, there's no impact in the gcc case. Explained by: bde Submitted by: Marius Strobl <marius@alchemy.franken.de> - aicasm.c: * minor change to teach it about the way icc spells "-nostdinc" Not approved by: gibbs (no reply to my mail) - bump __FreeBSD_version (lang/icc needs to know about the changes) Incarnations of this patch survive gcc compiles since a loooong time, I use it on my desktop. An icc compiled kernel works since Nov. 2003 (exceptions: snd_* if used as modules), it survives a build of the entire ports collection with icc. Parts of this commit contains suggestions or submissions from Marius Strobl <marius@alchemy.franken.de>. Reviewed by: -arch Submitted by: netchild
* Don't implement anything in the ffs family in <machine/cpufunc.h>bde2004-03-111-0/+4
| | | | | | | | | | | | | | | in the non-_KERNEL case. This "fixes" applications that include this "kernel-only" header and also include <strings.h> (or get <strings.h> via the default _BSD_VISIBLE pollution in <string.h>. In C++ there was a fatal error: the declaration specifies C linkage but the implementation gives C++ linkage. In C there was only a static/extern mismatch if the headers were included in a certain order order, and a partially redundant declaration for all include orders; gcc emits incomplete or wrong diagnostics for these, but only for compiling with -Wsystem-headers and certain other warning options, so the problem was usually not seen for C. Ports breakage reported by: kris
* Fixed insertion sort errors in prototype list.bde2004-03-051-20/+20
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* Removed garbage:bde2004-03-051-14/+0
| | | | | | | | | - completely unused things - all of rev.1.102 (C++ support). <sys/cdefs.h> is included by the prerequisite <sys/types.h>. __BEGIN_DECLS/__END_DECLS has no effect (except possibly if undefined behaviour is invoked using a hack like defining away __inline) since this header doesn't really support any extern functions.
* Fix syntax errors and wrong function prototypes in several MD headerle2004-03-051-3/+3
| | | | | | | | files when using non-GNUC compilers. PR: kern/58515 Submitted by: Stefan Farfeleder <stefan@fafoe.narf.at> Approved by: grog (mentor), obrien
* Backed out previous commit. This restores the warning about pessimizedbde2003-08-061-2/+2
| | | | | | | (short) types for the port arg of inb() (rev.1.56). The warning started working for u_short types with gcc-3.3. The pessimizations exposed by this been fixed except for the cx and oltr drivers where the breakage of the warning has been pushed to the drivers.
* Stop GCC from whining when people use a 16 bit port number for inb() and outb()phk2003-07-231-2/+2
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* Backout my last commit.davidxu2003-04-201-4/+4
| | | | Requested by: bde
* Don't return garbage in high 16 bits.davidxu2003-04-191-4/+4
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* Create inlines for ltr(sel), lldt(sel), lidt(addr) rather thanpeter2002-09-221-1/+26
| | | | functions that have one instruction.
* Provide in inline function for the (GNUC) assembler "hlt" instruction.markm2002-09-211-0/+7
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* Move SWTCH_OPTIM_STATS related code out of cpufunc.h. (This sort of statpeter2002-07-211-7/+0
| | | | gathering is not an x86 cpu feature)
* Cast to prevent "signed/unsigned comparison" warnings.markm2002-07-151-2/+2
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* Revive backed out pmap related changes from Feb 2002. The highlights are:peter2002-07-121-75/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - It actually works this time, honest! - Fine grained TLB shootdowns for SMP on i386. IPI's are very expensive, so try and optimize things where possible. - Introduce ranged shootdowns that can be done as a single IPI. - PG_G support for i386 - Specific-cpu targeted shootdowns. For example, there is no sense in globally purging the TLB cache for where we are stealing a page from the local unshared process on the local cpu. Use pm_active to track this. - Add some instrumentation for the tlb shootdown code. - Rip out SMP code from <machine/cpufunc.h> - Try and fix some very bogus PG_G and PG_PS interactions that were bad enough to cause vm86 bios calls to break. vm86 depended on our existing bugs and this was the cause of the VESA panics last time. - Fix the silly one-line error that caused the 'panic: bad pte' last time. - Fix a couple of other silly one-line errors that should have caused more pain than they did. Some more work is needed: - pmap_{zero,copy}_page[_idle]. These can be done without IPI's if we have a hook in cpu_switch. - The IPI handlers need some cleanup. I have a bogus %ds load that can be avoided. - APTD handling is rather bogus and appears to be a large source of global TLB IPI shootdowns for no really good reason. I see speedups of between 1.5% and ~4% on buildworlds in a while 1 loop. I expect to see a bigger difference when there is significant pageout activity or the system otherwise has memory shortages. I have backed out a few optimizations that I had been using over the last few days in order to be a little more conservative. I'll revisit these again over the next few days as the dust settles. New option: DISABLE_PG_G - In case I missed something.
* Rename pause() to ia32_pause() so it doesn't conflict with the pause()jhb2002-05-221-2/+2
| | | | | function defined in <unistd.h>. I didn't #ifdef _KERNEL it because the mutex implementation in libpthread will probably need this.
* Debug registers aren't selectors, so use saner names for the variables injhb2002-05-221-24/+24
| | | | the inline functions for reading and writing the debug registers.
* - Sort the pause() inline into the appropriate location.jhb2002-05-221-6/+25
| | | | - Add many missing prototypes to the non-GCC section.
* Rename cpu_pause() to pause(). Originally I was going to make this anjhb2002-05-221-1/+1
| | | | | | | | | MI API with empty cpu_pause() functions on other arch's, but this functionality is definitely unique to IA-32, so I decided to leave it as i386-only and wrap it in #ifdef's. I should have dropped the cpu_ prefix when I made that decision. Requested by: bde
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