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* Introduce the new kernel sub-tree x86 which should contain all the codeattilio2010-02-255-3719/+0
| | | | | | | | | | | | | | shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
* Previous solution appeared to be unsufficient. After additional testingmav2009-11-141-18/+18
| | | | | | | | | | | | | I have found that it is not only desktop CPUs problem. but mobile also. Probably AP on laptops just started initially at lower frequency, hiding the problem. Disable frequency validation by default, for systems with more then one CPU, until we can implement it properly. It looks like making more harm now then benefits. Add 'hw.est.strict' loader tunable to control it. Now my iXsystems Invincibook is able to run at 800MHz lowest frequency, instead of 1200MHz before, when 800MHz was incorrectly reported invalid.
* Retry only once, if BIOS is completely broken and gives zero freqs.mav2009-11-141-1/+1
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* Desktop Core2Duo/Core2Quad CPUs are unable to control frequency of singlemav2009-11-141-3/+12
| | | | | | | | | | | CPU core, only pair of them. As result, both cores are running on highest one of requested frequencies, and that is reported by status register. Such behavior confuses frequency validation logic, as it runs on only one core, as SMP is not yet launched, making EIST completely unusable. To workaround this, add check for validation result. If we haven't found at least two usable frequencies, then probably we are looking bad and have to trust data provided by BIOS as-is.
* Consolidate CPUID to CPU family/model macros for amd64 and i386 to reducejkim2009-09-101-8/+2
| | | | unnecessary #ifdef's for shared code between them.
* Import ACPICA 20090521.jkim2009-06-053-3/+6
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* Remove unused variables.brueffer2009-05-121-4/+1
| | | | | Found with: Coverity Prevent(tm) CID: 4285, 4286
* Extend comment in copyright notice as requested by author.mr2009-03-291-1/+1
| | | | Submitted by: G.Otsuji
* Add support for Phenom (Family 10h) to cpufreq.mr2009-03-281-0/+515
| | | | | | | Its a newer version provided by the author than in the PR. PR: kern/128575 Submitted by: Gen Otsuji annona2 [at] gmail.com
* Include a missing header file.jkim2009-01-221-0/+1
| | | | Reported by: thompsa, "build universe"
* Replace couple of strcmp(cpu_vendor, "foo") with cpu_vendor_id for i386jkim2009-01-221-1/+1
| | | | and hide i386-specific code under #ifdef.
* Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.jkim2009-01-051-4/+0
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* Remove an unused variable.jkim2008-11-261-2/+1
| | | | | Found with: Coverity Prevent(tm) CID: 3677
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-9/+12
| | | | Reviewed by: jhb, peter (early amd64 version)
* Add Pentium D cores into the list that can't handle 12.5% and 25%sobomax2008-11-261-1/+4
| | | | | | | | | throttle. My SMP kernel hangs when one of those is selected by powerd. Errata AA21 here: ftp://download.intel.com/design/PentiumXE/specupdt/31030717.pdf MFC after: 2 weeks
* Do not use PowerNow! if FID or VID is missing.jkim2008-10-211-1/+1
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* Use power management information for AMD CPUs from identcpu.c.jkim2008-10-211-17/+1
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* Add a proper detach method to the est(4) driver using cpufreq_unregister().jhb2008-09-101-3/+6
| | | | MFC after: 1 week
* Fail detach if cpufreq_unregister() fails.jhb2008-08-282-4/+3
| | | | MFC after: 1 week
* Disable the code to generate a simple table from the status MSR by default.jhb2008-08-261-0/+5
| | | | This can be enabled by setting the 'hw.est.msr_info' tunable to 1.
* If we are unable to obtain a frequency list from either ACPI or the staticjhb2008-08-231-1/+88
| | | | | | | | tables, then attempt to build a simple list containing just the high and low frequencies based on the current CPU frequency calculated during boot and the contents of the MSR. MFC after: 1 month
* Attach the cpufreq child devices with specific orders to enforce relativejhb2008-08-134-4/+4
| | | | | | | | | | | | | | priority of some of the drivers that manage the same state (e.g. ichss0 vs est0). Specifically, powernow, est, and p4tcc are added at order 10, ichss at order 20, and smist at order 30. Previously, some laptops were seeing both ichss0 and est0 attaching and stomping on each other. XXX: This isn't quite ideal, but works with the existing hacks, I think what we really want instead is a single "speedstep0" device for CPUs that the ichss, est, and smist drivers probe (but with differing priorities). MFC after: 1 week
* After probing the available frequency settings, restore the CPU to run atjhb2008-05-301-17/+5
| | | | | | | | | | whatever frequency it started at instead of always picking the highest frequency. The first version of this driver attempted to do this, but it set the speed to the first frequency in the list rather than the value it had saved. MFC after: 1 week Discussed with: rpaulo, phk
* Remove unused variable saved_id16.rpaulo2008-05-021-2/+0
| | | | | | Pointy hat to: me Pointed out by: jhb MFC after: 1 week
* A cautionary XXX comment about seemingly bogus errata checks.phk2008-03-171-0/+8
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* Increase time we wait for things to settle to 1 millisecond,phk2008-03-171-2/+16
| | | | | | | 10 microseconds is too short. Always set the cpu to the highest frequency so that we get through boot and don't handicap cpus where powerd(8) is not used.
* Revert last commit and stop committing before morning tea.phk2008-03-171-26/+5
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* Increase time we wait for things to settle to 1 millisecond,phk2008-03-171-5/+26
| | | | | | | 10 microseconds is too short. Always set the cpu to the highest frequency so that we get through boot and don't handicap cpus where powerd(8) is not used.
* Use correct bitmask for identifying chip family.phk2008-03-171-1/+1
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* - Don't execute cpuid to fetch the features. We already have the featuresjhb2008-03-101-5/+5
| | | | | | | | | | present in cpu_feature2. Also, use CPUID2_EST rather than a magic number. - Don't free the ACPI settings list in detach if we are going to fail the request. Otherwise an attempt to kldunload est would free the array but the driver would keep trying to use it. MFC after: 1 week
* In est_acpi_info(), initialize count before passing its pointer togibbs2008-03-011-0/+1
| | | | | | | | | | CPUFREQ_DRV_SETTINGS(). The value of count on input is used to prefent overflow of the settings buffer passed into CPUFREQ_DRV_SETTINGS(). This corrects the "est: CPU supports Enhanced Speedstep, but is not recognized." error on my system. MFC after: 1 week
* Validate the id16 values gathered from ACPI (previously a TODO item).rpaulo2008-02-281-17/+59
| | | | | | | | | | Style changes by me and njl. Approved by: njl (mentor) Reviewed by: njl (mentor) Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp> PR: 119350 MFC after: 1 week
* Use bus_dma to get a page in the first 4 GB. Since the physical addressnjl2007-06-171-17/+70
| | | | | | | | of the magic string is passed in a 32-bit register, we can't use high memory in the PAE case. This also eliminates a use of vtophys(). Tested by: Jeff Shimbo <jts767 / gmail.com> MFC after: 1 week
* o introduce a flags 'errata' for HW bugs onto the softc.bruno2007-01-231-42/+97
| | | | | | | | | | | | | o remove errata_a0 and introduce the corresponding flags into 'errata'. o introduce a new errata for K8, namely some platform might set the PENDING_BIT but aren't able to unset it, also don't loop forever waiting PENDING_BIT being cleared. o try to introduce a workaround for the PENDING_BIT stuck problem, o support now half multipliers for K8. Tested by: Abdullah Al-Marrie Approved by: njl
* Since DELAY() was moved, most <machine/clock.h> #includes have beenphk2006-05-161-1/+0
| | | | unnecessary.
* Add support for the VIA C7-M processor family.njl2006-05-111-14/+160
| | | | | | | | | Remove an unnecessary check of the table's bus clock. CPUs that support this feature export only the high/low settings via the MSR, packed into 32 bits. Hardware from: Centaur Technologies MFC after: 1 week
* Add frequency-voltage tables for Intel 778, 758, 773, 753, and 733Jcperciva2006-02-251-0/+210
| | | | | | processors. Obtained from: Intel Datasheet 302189-008
* Like acpi_throttle, set frequency to 100% in attach. Some BIOSen may setnjl2005-10-231-0/+8
| | | | this value lower, making the system quite slow after booting.
* Print cpu_vendor and the MSR value if we don't support this processorcperciva2005-07-311-1/+1
| | | | | | even though we're not asking people to contact us. Requested by: njl
* Remove the instruction to "contact the maintainer" for unrecognizedcperciva2005-07-311-3/+1
| | | | | CPUs. Intel refuses to give me the information I need, and getting more emails about this doesn't help.
* Add a driver for SMI-based SpeedStep. The hardware supports two frequencynjl2005-04-191-0/+460
| | | | | | | | | | settings and is an older version of the same design used for ICH SpeedStep. It is only known to be available on PIIX4 chipsets. Many thanks to Bruno Ducrot for writing the driver and Jon Noack for testing. Submitted by: Bruno Ducrot
* Properly terminate the table generated from ACPI info. The cpufreqnjl2005-04-101-6/+6
| | | | | settings are length-counted while the EST table is null-terminated. This fixes extra garbage states being reported with ACPI probing.
* Advertise p4tcc via acpi_get_features() _PDC support.njl2005-04-101-0/+18
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* Add support for _PDC/_OSC by advertising that we support direct access tonjl2005-04-041-1/+21
| | | | | the PERF_CTL/STS MSRs via the new acpi_get_features() method. This should allow newer systems to use SpeedStep.
* Remove check of numpst to allow more K8 variants to attach. The othernjl2005-03-311-1/+7
| | | | | | | | checks, including cpuid_is_k7(), will catch CPUs that really don't support this method. Submitted by: Bruno Ducrot Tested by: Jari Kirma (kirma cs.hut.fi)
* Add the powernow driver, which handles AMD Mobile Athlon PowerNow! (k7)njl2005-03-271-0/+928
| | | | | | | | | and AMD Cool&Quiet PowerNow! (k8) cpufreq control. This driver is enabled for both i386 and amd64 architectures. It has both acpi and legacy BIOS attachments. Thanks to Bruno Ducrot for writing this driver and Jung-uk Kim for testing. Submitted by: Bruno Ducrot (ducrot:poupinou.org)
* Add support for probing EST settings from ACPI. This should handle morenjl2005-03-211-77/+166
| | | | | | modern CPUs that have multiple VID#s that aren't detectable via public methods. We use the control value from acpi_perf as the id16 for setting a given frequency.
* Make a pass through all drivers checking specs for desired behavior onnjl2005-02-272-0/+15
| | | | | | | SMP systems. It appears all drivers except ichss should attach to each CPU and that settings should be performed on each CPU. Add comments about this. Also, add a guard for p4tcc's identify method being called more than once.
* Correct an off-by-one error in the number of settings est announces.njl2005-02-241-4/+3
| | | | The extraneous "0" state was not fatal but useless.
* Import a rewrite of p4tcc for the cpufreq(4) framework. This includesnjl2005-02-231-189/+197
| | | | | | a bugfix of clearing the On-Demand flag when going back to 100%. It has been tested and works on an IBM R32. Note original work done by Ted Unangst and sobomax@.
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