| Commit message (Collapse) | Author | Age | Files | Lines |
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First, we compare mode table data against minimum value. If the mode table
does not make sense, we set the minimum in the mode info. When we actually
set the mode, we try VESA BIOS function and compare it against the previous
value. If it makes more sense, update the information.
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in 6-bit mode. Although we have to check non-VGA compatibility bit here,
it seems there are too many broken VESA BIOSes out to rely on it.
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Although we do not use them all directly, it seems VGA render may access
unmapped memory region and cause kernel panic.
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not want to write a useless zero to inaccessible memory region.
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PR: kern/144713
Submitted by: gcooper
MFC after: 2 weeks
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appear to be necessary on either sparc64 or powerpc, and is a
concurrency nightmare.
Reviewed by: marius
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- Do not try to enable CCC if it is not supported.
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Andrew Turner. The kernel supports the LN2410SBC evaluation board,
and likely others. These parts (or similar ones) are in some open
hardware designs for phones.
Submitted by: Andrew Turner
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- Update copyright to 2010.
- Add new debug code for RV2P block.
- Improve output formatting for various debug functions.
MFC after: 2 weeks
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Submitted by: pyunyh
MFC after: 2 weeks
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Reported by: tinderbox
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set early enough that we don't need to do these hacks anymore.
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those modern drivers.
Reviewed by: imp (and suggested by imp)
MFC after: 3 days
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- Don't leak slice resources when mxge_alloc_rings() fails
- Start taskq threads only after we know attach will succeed. At
boot time, taskqueue_terminate() will loop infinately, waiting
for the threads to exit, and hang the system.
Submitted by: Panasas
MFC After: 3 days
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seconds. Oops.
Untangle some of the confusion about what role means when it's in the FCPARAM/SDPARAM
or isp_fc/isp_spi structures. This fixed a problem about seeing targets appear if you've
turned off autologin and find them, or rather don't, via camcontrol rescan.
MFC after: 1 month
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It's hard to know when the mail box register write will get flushed to
the hardware and it may take longer.
Pointed out by: scottl
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than amd64.
Sponsored by: Sandvine Incorporated
Submitted by: emaste
MFC: 2 weeks
X-MFC: r205160
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configuration space on Yukon Ultra(88E8056) such that accesses to
these registers were NOPs which in turn make msk(4) instable on
this controller. Use indirect access method to access
PCI_OUR_REG_[1-5] registers. This should fix a long standing
instability bug which prevented msk(4) working on Yukon Ultra.
Special thanks to koitsu who gave me remote access to his system.
PR: kern/114631, kern/116853
MFC after: 1 week
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arcconf tool by Adaptec already seems to use for identifying the
Serial Number of the devices.
Some simple things (like FIB setup and bound checks) are retrieved
from the Adaptec's driver, but this implementation is quite different
because it does use the normal buffer dmat area for loading segments
and not a special one (like the Adaptec's one does).
Sponsored by: Sandvine Incorporated
Discussed with: emaste, scottl
Reviewed by: emaste, scottl
MFC: 2 weeks
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Reported by: imp
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Reported by: Sergey V. Dyatko <sergey.dyatko@gmail.com>
MFC after: 3 days
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Slightly modified version of the submitted patch.
PR: 143427
Submitted by: Mamoru Sumida <msumida@mvc.biglobe.ne.jp>
MFC after: 3 days
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have the delayed function take an argument as to the offset
to the SCTP header. This allows it to work for V4 and V6.
This of course means changing all callers of the function
to either pass the header len, if they have it, or create
it (ip_hl << 2 or sizeof(ip6_hdr)).
PR: 144529
MFC after: 2 weeks
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MFC after: 3 days
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These behave just like g45 for agp.
Tested by: Torfinn Ingolfsen
MFC after: 3 days
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Yukon FE and Yukon Ultra2. These controllers provide very simple
checksum computation mechanism and it requires additional pseudo
header checksum computation in upper stack. Even though I couldn't
see much performance difference with/without Rx checksum offloading
it may help notebook based controllers.
Actually controller can compute two checksum value by giving
different starting position of checksum computation on received
frame. However, for long time, Marvell's checksum offloading engine
have been known to have several silicon bugs so don't blindly trust
computed partial checksum value. Instead, compute partial checksum
twice by giving the same checksum computation position and compare
the result. If the value is different it's clear indication of
hardware bug. This configuration lose IP checksum offloading
capability but I think it's better to take safe route.
Note, Rx checksum offloading for Yukon XL was still disabled due to
known silicon bug.
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index of status block is read first before acknowledging the
interrupts. Otherwise bge(4) may get stale status block as
acknowledging an interrupt may yield another status block update.
Reviewed by: marius
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PR: kern/102211
Submitted by: yoichi
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- Drain our tasks from the ieee80211 taskqueue
- Add more IDs
Submitted by: Akinori Furukoshi
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PR: usb/144414
Submitted by: Hans Petter Selasky
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Submitted by: Alexander Best
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Submitted by: Paul B Mahol
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Submitted by: Hans Petter Selasky
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ISOCHRONOUS transfers
Submitted by: Hans Petter Selasky
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because the chip doesn't do this by itself.
Submitted by: Hans Petter Selasky
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default.
Submitted by: Hans Petter Selasky
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PR: usb/144201
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is issued at the beginning of the initial IN/OUT data transfers. Reason
unknown, probably firmware fault. Now the stall is only cleared on data
transfer errors.
PR: usb/144199
Submitted by: Hans Petter Selasky
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other modules can generate USB descriptors.
- extend the vendor specific request function by one length pointer argument,
because not all descriptors store the length in the first byte. For example
HID descriptors.
Submitted by: Hans Petter Selasky
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Submitted by: Hans Petter Selasky
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Submitted by: Giovanni Trematerra
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non-debug cases.
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