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* Correct PCI device description.hselasky2016-02-101-1/+1
| | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>
* EHCI: Correct address of EHCI_USBMODE_LPM register is 0xC8, not 0xA8.mmel2016-01-301-1/+1
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* EHCI: Make core reset and port speed reading more generic.mmel2016-01-285-40/+107
| | | | | | | | | | | | | | | | | Use driver settable callbacks for handling of: - core post reset - reading actual port speed Typically, OTG enabled EHCI cores wants setting of USBMODE register, but this register is not defined in EHCI specification and different cores can have it on different offset. Also, for cores with TT extension, actual port speed must be determinable. But again, EHCI specification not covers this so this patch provides function for two most common variant of speed bits layout. Reviewed by: hselasky Differential Revision: https://reviews.freebsd.org/D5088
* Improve attachment of the ehci_mv driverzbb2016-01-201-14/+24
| | | | | | | | | | | | Driver was modified to ensure it attaches properly to "marvell,orion-ehci" node, which doesn't have error interrupt line defined. Neccessary ofw_compat_data struct was added and probe procedure was altered. Reviewed by: andrew, ian Obtained from: Semihalf Sponsored by: Stormshield Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Differential revision: https://reviews.freebsd.org/D4369
* Move ohci files to their proper place in the tree for atmel.imp2016-01-162-493/+0
| | | | | | | Fix when it is included (we don't have a at91rm9200 device). From a similar patch in the PR, with tweaked names. PR: 206229
* Fix for directly connected FULL or LOW speed USB devices.hselasky2016-01-051-6/+21
| | | | | Found by: Sebastian Huber <sebastian.huber@embedded-brains.de> MFC after: 1 week
* Ads support to the xhci pci attachment to use MSI-X interrupts whenandrew2015-12-242-2/+30
| | | | | | | | | | | | | | available. As with MSI interrupts these can be disabled by setting hw.usb.xhci.msix to 0 in the loader. MSI-X interrupts are needed on some hardware, for example the Cavium ThunderX only supports them, and with this we don't fall back to polling. PR: 204378 Reviewed by: hselasky, jhb MFC after: 1 week (after r292669) Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D4698
* Fix compile warning about shifting signed negative constant.hselasky2015-11-231-1/+1
| | | | MFC after: 3 days
* Avoid using the bounce buffer when the source or destination buffer ishselasky2015-11-082-39/+143
| | | | | | | | 32-bits aligned. Merge the two bounce buffers into a single one. Some rough tests showed that the DWC OTG throughput on RPI2 increased by 10% after this patch. MFC after: 1 week
* Reduce the DWC OTG interrupt load by not reading all the host channelhselasky2015-10-301-6/+11
| | | | | | | | | status registers for every interrupt. Check a common host channel status interrupt register first, then conditionally read the individual host channel status registers. Submitted by: Sebastian Huber <sebastian.huber@embedded-brains.de> MFC after: 1 week
* Add quirk for USB 3.0 PCI device.hselasky2015-10-191-0/+3
| | | | | | Submitted by: philipp.maechler@mamo.li PR: 203650 MFC after: 1 week
* Add support for Fresco Logic USB 3.0 host controller.kevlo2015-10-081-6/+11
| | | | | | | Fresco Logic hosts advertise MSI, but fail to actually generate MSI interrupts. We have to disable MSI use. Reviewed by: hselasky
* Add quirk for USB 3.0 PCI device.hselasky2015-10-081-0/+1
| | | | | Submitted by: Gary Jennejohn <gj@freebsd.org> MFC after: 1 week
* Add Cavium ThunderX xHCI controller PCI IDemaste2015-09-151-0/+3
| | | | | | | | | There is an issue with interrupts at the moment, but it works with polling mode set (hw.usb.xhci.use_polling=1). Reviewed by: hselasky Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3665
* Correct PCI ID.hselasky2015-09-141-1/+1
| | | | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 1 month PR: 202807
* Add support for the dwc usb in the HiSilicon hi6220 in the HiKey board. Forandrew2015-09-011-0/+97
| | | | | | | | this we need to force the driver into host mode, as without this the driver fails to detect any devices. Relnotes: yes Sponsored by: ABT Systems Ltd
* Add new PCI ID.hselasky2015-09-011-0/+7
| | | | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 1 month PR: 202807
* Fixes for HIGH speed ISOCHRONOUS traffic. HS ISOCHRONOUS traffic athselasky2015-08-152-216/+236
| | | | | | | | | intervals less than 250us was not handled properly. Add support for high-bandwidth ISOCHRONOUS packets. USB webcams, USB audio and USB DVB devices are expected to work better. High-bandwidth INTERRUPT endpoints is not yet supported. MFC after: 2 weeks
* Handle NYET high speed tokens and predict NAK'ing is up next.hselasky2015-08-141-7/+13
| | | | MFC after: 2 weeks
* Minor code refactor to avoid duplicating code.hselasky2015-08-141-18/+9
| | | | MFC after: 2 weeks
* Improve the realtime properties of USB transfers for embedded systemshselasky2015-08-141-4/+10
| | | | | | | | | | | | | | | | | | | | like RPI-B and RPI-2. Description of problem: USB transfers can process data in their callbacks sometimes causing unacceptable latency for other USB transfers. Separate BULK completion callbacks from CONTROL, INTERRUPT and ISOCHRONOUS callbacks, and give BULK completion callbacks lesser execution priority than the others. This way USB audio won't be interfered by heavy USB ethernet usage for example. Further serve USB transfer completion in a round robin fashion, instead of only serving the most CPU hungry. This has been done by adding a third flag to USB transfer queue structure which keeps track of looping callbacks. The "command" callback function then decides what to do when looping. MFC after: 2 weeks
* Limit the number of times we loop inside the DWC OTG poll handler tohselasky2015-07-311-1/+7
| | | | | | | avoid starving other fast interrupts. Fix a comment while at it. MFC after: 1 week Suggested by: Svatopluk Kraus <onwahe@gmail.com>
* Optimise the DWC OTG host mode driver's receive path:hselasky2015-07-282-50/+30
| | | | | | | | | Remove NAKing limit and pause IN and OUT transactions for 125us in case of NAK response for BULK and CONTROL endpoints. This gets the receive latency down and improves USB network throughput at the cost of some CPU usage. MFC after: 1 month
* - Move the remainder of host controller capability registers reading frommarius2015-07-272-82/+77
| | | | | | | | | | | | xhci_start_controller() to xhci_init(). These values don't change at run- time so there's no point of acquiring them on every USB_HW_POWER_RESUME instead of only once during initialization. In r276717, reading the first couple of registers in question already had been moved as a prerequisite for the changes in that revision. - Identify ASMedia ASM1042A controllers. - Use NULL instead of 0 for pointers. MFC after: 3 days
* Optimise the DWC OTG host mode driver's transmit path:hselasky2015-07-163-114/+77
| | | | | | | | | | | | | | | | | | | | | | | | 1) Use the TX FIFO empty interrupts to poll the transmit FIFO usage, instead of using own software counters and waiting for SOF interrupts. Assume that enough FIFO space is available to execute one USB OUT transfer of any kind when the TX FIFO is empty. 2) Use the host channel halted event to asynchronously wait for host channels to be disabled instead of waiting for SOF interrupts. This results in less turnaround time for re-using host channels and at the same time increases the performance. The network transmit performance measured by "iperf" for the "RPi-B v1 2011/12" board, increased from 45MBit/s to 65Mbit/s after applying the changes above. No regressions seen using: - High Speed (BULK, CONTROL, INTERRUPT) - Full Speed (All transfer types) - Low Speed (Control and Interrupt) MFC after: 1 month Submitted by: Daisuke Aoyama <aoyama@peach.ne.jp>
* Fix for control endpoint handling in the DWC OTG driver. The datahselasky2015-06-021-56/+52
| | | | | | | | stage processing is only allowed after the setup complete event has been received. Else a race may occur and the OUT data can be corrupted. While at it ensure resetting a FIFO has the required wait loop. MFC after: 3 days
* Fix for DWC OTG device side isochronous transfers. The even or oddhselasky2015-05-191-2/+31
| | | | | | isochronous frame bit needs to be flipped. MFC after: 3 days
* Make the FIFO configuration a bit more flexible for the DWC OTG inhselasky2015-05-182-22/+22
| | | | device side mode.
* Disable multi process interrupts, because the current code doesn't usehselasky2015-04-231-9/+7
| | | | | | | them. Else we can end up in an infinite interrupt loop in USB device mode. MFC after: 3 days
* Modify the return value of the uhci/ehci/xhci PCI probe routines toneel2015-04-133-3/+3
| | | | | | | | | | | 'BUS_PROBE_DEFAULT'. This allows bhyve's 'ppt' driver to claim ownership of the device and pass it through to the guest. In the common case where there are no competing drivers for USB controllers this change is a no-op. Reviewed by: hselasky MFC after: 2 weeks
* Add support for enabling the USB on the Raspberry Pi boards when it hasn'tandrew2015-03-082-11/+46
| | | | | | | | | | | | | been done by U-Boot. This allows the USB to work when we load the kernel directly. No dma sync is performed after these operations as the data we read/write is not used by the cpu after the calls to the maimbox driver. Differential Revision: https://reviews.freebsd.org/D1940 Reviewed by: imp, Michal Meloun (meloun AT miracle.cz) MFC after: 1 Week Sponsored by: ABT Systems Ltd
* Sort and remove unnecessary headers.loos2015-03-031-14/+4
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* Add quirk for USB 3.0 controllers which don't support 64-bit DMA.hselasky2015-03-031-1/+12
| | | | | MFC after: 3 days Submitted by: Gary Jennejohn <gljennjohn@gmail.com>
* Add quirk to disable 64-bit XHCI DMA after r276717.hselasky2015-03-023-6/+11
| | | | | Requested by: Gary Jennejohn <gljennjohn@gmail.com> MFC after: 3 days
* Ensure that the XHCI driver will refresh the control endpoint settingshselasky2015-02-241-0/+7
| | | | | | | when re-enumerating a FULL speed device. Else the wrong max packet setting might be used when trying to re-enumerate a FULL speed device. MFC after: 3 days
* Add support for the DWC OTG v2 chipset found in the STM32F4 series ofhselasky2015-02-232-11/+48
| | | | | | | processors. Make sure we pullup the data lines in device mode when we power on the port. MFC after: 1 week
* Try to resolve infinite interrupts by clearing an undocumentedhselasky2015-02-171-1/+2
| | | | | | | | | interrupt status bit. According to the UHCI controller specification the host controller halted interrupt is non-maskable. PR: 156596 Tested by: adrian @ MFC after: 1 week
* Handle VBUS error interrupts.hselasky2015-02-161-1/+8
| | | | | | Submitted by: SAITOU Toshihide <toshi@ruby.ocn.ne.jp> PR: 190471 MFC after: 1 week
* Fix DMA address casts. Regression issue after r278279.hselasky2015-02-091-2/+2
| | | | MFC after: 3 days
* Section 3.2.9 in the XHCI specification about control transfers sayshselasky2015-02-021-1/+11
| | | | | | | | | that we should use a normal-TRB if there are more TRBs extending the data-stage TRB. Add a dedicated state bit to the internal USB transfer flags to handle this case. Reported by: Kohji Okuno <okuno.kohji@jp.panasonic.com> MFC after: 1 week
* Revise the arm bus_space implementation to avoid dereferencing the tag onian2015-01-211-17/+17
| | | | | | | | | | | | | | | | | every operation to retrieve the bs_cookie value almost nothing actually uses. The bus_space struct contains a private data pointer (poorly named bs_cookie, now renamed to bs_privdata) which is used only by a few old armv4 xscale implementations. The bus_space functions were all defined to take this value as the first parameter instead of the bus_space_tag_t, requiring all the inline macro and function expansions to dereference the tag to pass it to another function, which never uses it. Now all the functions take the tag as the first parameter and retrieve the privdata if they need it. Also fix a couple bus_space_unmap() implementations that were calling kva_free() instead of pmap_unmapdev(). Discussed with: cognet
* Resolve a special case deadlock: When two or more threads arehselasky2015-01-131-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | simultaneously detaching kernel drivers on the same USB device we can get stuck in the "usb_wait_pending_ref_locked()" function because the conditions needed for allowing detach are not met. The "destroy_dev()" function waits for all system calls involving the given character device to return. Character device system calls may lock the USB enumeration lock, which is also held when "destroy_dev()" is called. This can sometimes lead to a deadlock not noticed by WITNESS. The current solution is to ensure the calling thread is the only one holding the USB enumeration lock and prevent other threads from getting refs while a USB device detach is ongoing. This turned out not to be sufficient. To solve this deadlock we could use "destroy_dev_sched()" to schedule the device destruction in the background, but then we don't know when it is safe to free() the private data of the character device. Instead a callback function is executed by the USB explore process to kill off any leftover USB character devices synchronously after the USB device explore code is finished and the USB enumeration lock is no longer locked. This makes porting easier and also ensures us that character devices must eventually go away after a USB device detach. While at it ensure that "flag_iserror" is only written when "priv_mtx" is locked, which is protecting it. MFC after: 5 days
* Fix misleading comment.hselasky2015-01-081-1/+1
| | | | | MFC after: 1 week Reported by: rpaulo@
* Fix handling of an error case when the MUSB driver is operating in USBhselasky2015-01-081-6/+11
| | | | | | | device side mode. MFC after: 1 week Reported by: br@
* Add 64-bit DMA support in the XHCI controller driver.hselasky2015-01-0521-56/+83
| | | | | | | - Fix some comments and whitespace while at it. MFC after: 1 month Submitted by: marius@
* Make a bunch of USB debug SYSCTLs tunable, so that their value(s) canhselasky2015-01-057-8/+8
| | | | be set before the USB device(s) are probed.
* Allow systems having a page size greater than 4K to use fewerhselasky2014-12-301-3/+15
| | | | | | | | | scatter-gather XHCI TRB entries for its payload data. The XHCI controller can handle at least 65536 bytes per scatter-gather list entry. MFC after: 1 week Suggested by: Kohji Okuno <okuno.kohji@jp.panasonic.com>
* Add missed flushing of data which can happen when "xhci_configure_mask()"hselasky2014-12-301-4/+9
| | | | | | | | is called from "xhci_configure_reset_endpoint()". Ensure the 3-strikes error feature is always enabled except for ISOCHRONOUS transfers. MFC after: 1 week Suggested by: marius@
* Improve/fix interrupt allocation/setup/release:marius2014-12-272-22/+24
| | | | | | | | | | | | | | - Simplify MSI allocation to what is actually needed for a single one. - Release the MSI and the corresponding bus resource as appropriate when either the interrupt resource cannot be allocated or setting up the interrupt fails. - Error out when interrupt allocation or setup fails and polling is disabled. - Release the MSI after the corresponding bus resource so the former is not leaked on detach. - Remove a redundant softc member. MFC after: 3 days
* Add port routing support for Wildcat Point.hselasky2014-12-081-0/+1
| | | | | PR: 195793 MFC after: 1 week
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