| Commit message (Collapse) | Author | Age | Files | Lines |
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Fix for control endpoint handling in the DWC OTG driver. The data
stage processing is only allowed after the setup complete event has
been received. Else a race may occur and the OUT data can be corrupted.
While at it ensure resetting a FIFO has the required wait loop.
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Fix for DWC OTG device side isochronous transfers. The even or odd
isochronous frame bit needs to be flipped.
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Disable multi process interrupts, because the current code doesn't use
them. Else we can end up in an infinite interrupt loop in USB device
mode.
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Add quirk for USB 3.0 controllers which don't support 64-bit DMA.
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Add quirk to disable 64-bit XHCI DMA after r276717.
Requested by: Gary Jennejohn <gljennjohn@gmail.com>
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Add support for the DWC OTG v2 chipset found in the STM32F4 series of
processors. Make sure we pullup the data lines in device mode when we
power on the port.
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Ensure that the XHCI driver will refresh the control endpoint settings
when re-enumerating a FULL speed device. Else the wrong max packet
setting might be used when trying to re-enumerate a FULL speed device.
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Handle VBUS error interrupts.
PR: 190471
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r277472, r277473, r277474, r277475, r277476, r277477, r277478, r277479,
r277480, r277512, r277516:
Add inline implementations of arm bus_space_read/write_N().
Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.
Use the explicit member initializer style to init the bus_space struct.
Use arm/bus_space-v6.c for all armv6 systems
Consolidate many identical implementations of bus_space to a single
common tag and implementation shared by armv4 and armv6.
Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct so that they all fit in a single cache line.
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Fix DMA address casts.
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Section 3.2.9 in the XHCI specification about control transfers says
that we should use a normal-TRB if there are more TRBs extending the
data-stage TRB. Add a dedicated state bit to the internal USB transfer
flags to handle this case.
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Resolve a special case deadlock: When two or more threads are
simultaneously detaching kernel drivers on the same USB device we can
get stuck in the "usb_wait_pending_ref_locked()" function because the
conditions needed for allowing detach are not met.
While at it ensure that "flag_iserror" is only written when "priv_mtx"
is locked, which is protecting it.
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Add 64-bit DMA support in the XHCI controller driver.
- Fix some comments and whitespaces while at it.
- Add support for PAE.
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Fix handling of an error case when the MUSB driver is operating in USB
device side mode.
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- Add IDs for Intel Patsburg USB 2.0 controller.
- Add the Intel BayTrail USB device which needs port routing for USB 3.0.
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Various XHCI fixes and improvements:
- Improve and fix MSI interrupt allocation, setup and release.
- Add missed flushing of data which can happen when "xhci_configure_mask()"
is called from "xhci_configure_reset_endpoint()". Ensure the 3-strikes
error feature is always enabled except for ISOCHRONOUS transfers.
- Allow systems having a page size greater than 4K to use fewer
scatter-gather XHCI TRB entries for its payload data. The XHCI
controller can handle at least 65536 bytes per scatter-gather list
entry.
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Add port routing support for Wildcat Point.
PR: 195793
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Add bunch of PCI IDs of Intel Wildcat Point (9 Series) chipsets.
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Remove unused defines.
Fix some device_printf's that were missing '\n' at the end or had
spelling errors.
PR: 145319
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- Fix XHCI driver for devices which have more than 15 physical root HUB
ports. The current bitmap array was too small to hold more than 16
bits and would at some point toggle the context size, which then would
trigger an enumeration fault and cause a fallback to the EHCI
companion controller, if any.
- Make sure we always set the maximum number of valid contexts.
- Set default cycle state in case of early interrupts.
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Some XHCI hardware requires dropping the endpoint context before
adding it again.
Approved by: re, glebius
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Rename driver name a bit to avoid unit number confusion in dmesg.
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- Implement fast interrupt handler to save CPU usage.
- Cleanup some register reads and writes to use existing register
access macros.
- Ensure code which only applies to the control endpoint is not run
for other endpoints in the data transfer path.
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Add description of two EHCI PCI IDs.
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Split the XHCI TRB allocations into smaller parts, so that we don't
end up allocating contiguous busdma buffers above PAGE_SIZE bytes.
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Improve support for Intel Lynx Point USB 3.0 controllers by using the
USB 2.0 port mask in addition to the USB 3.0 port mask. The hardware
does not always accept when writing -1U to the port switching
registers.
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Improve support for Intel Lynx Point USB 3.0 controllers by masking
the port routing bits like done in Linux.
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Avoid the USB device disconnected and controller shutdown clutter on system
shutdown by putting the former under !rebooting and turning the latter into
debug messages.
Reviewed by: hps
Sponsored by: Bally Wulff Games & Entertainment GmbH
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Resolve a deadlock setting the USB configuration index from userspace
on USB HUBs by moving the code into the USB explore threads. The
deadlock happens because child devices of the USB HUB don't have the
expected reference count when called from outside the explore
thread. Only the HUB device itself, which the IOCTL interface locks,
gets the correct reference count.
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Make WITNESS happy by giving USB mutexes different names.
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Multiple fixes for FULL and LOW speed USB transfers going through
the DWC OTG as split transactions. INTERRUPT transfers should have
a higher chance of success after this series of patches and the
chance of data loss should be reduced.
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Add some more spinlocks to protect the state of the USB transfer
queue. Rename some functions to indicate locking requirements.
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- Fix a bug where the TLBPC value was forced to being odd for IN
direction isochronous transfers.
- Remove setting of fields which does not belong to the respective
TRBs. These fields are currently set as zero and this is more a
cosmetic change.
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r265806, r265872, r266012 and r266394:
- Multiple DWC OTG host mode related fixes, improvements and optimisations.
- Add full support for ISOCHRONOUS transfers to the DWC OTG driver.
- Use the interrupt filter to handle basic USB FIFO interrupts.
- Fixed unbalanced unlock in case of "dwc_otg_init_fifo()" failure.
- Add common spinlock to the USB bus structure.
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Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead
define a few imx_ccm_foo() functions that are implemented by the imx51
or imx6 ccm code.
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r262606
Initial import of Linux/Vendor DTS files for various embedded boards.
Initial import of DTS files from Linux
Correct initial import script
New AT91 devices or fdt probe added to existing devices. Some of these
are just stubs for testing the new dts.
- nand
- SDRAMC
- shdwc
- tcb
- usb host and gadget
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Remove FreeBSD 6 support from atmel usb controllers.
Add Vybrid drivers for:
- Enhanced Direct Memory Access Controller (eDMA)
- Direct Memory Access Multiplexer (DMAMUX)
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Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.
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Add configuration for the Freescale i.MX53 Quick Start Board.
Add the Raspberry Pi BSC (I2C compliant) controller driver.
Add Radxa Rock board (by radxa.com) support.
Digi-CCWMX53: enable ffec and uart, USB.
Add support for Freescale Vybrid Family VF600
Move and rename dwc otg driver to more generic one as it appears to work
for rk3188 SoC based board too.
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Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel
LynxPoint USB 3.0 controllers found in MacBookPro 2013's.
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Correct IMOD default value according to comment.
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Fix for infinite XHCI reset loops when the set address USB request fails.
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In sys/dev/usb/controller/uss820dci.c, similar to r261977, fix a warning
about uss820dci_odevd being unused, by adding it to the part that
handles getting descriptors.
Reported by: loos
Reviewed by: hselasky
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Fix minor logical error in the XHCI driver. Set correct SETUP packet
direction value.
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Add new PCI ID for hardware which needs port routing for USB 3.0.
PR: usb/186811
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Issue doorbell twice before finally freeing the DMA descriptors. This
should fix DMA descriptor caching issues seen with the EHCI controller
found in Google Chromebook C720 during removal and insertion of USB
devices.
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In sys/dev/usb/controller/musb_otg.c, fix a warning about musbotg_odevd
being unused, by adding it to the part that handles getting descriptors.
Reviewed by: hselasky
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Adjust the DMA delay logic so that the DMA delay does not become too small.
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Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
Similar to the (1 << 31) case it is not defined to do (2 << 30).
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
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