summaryrefslogtreecommitdiffstats
path: root/sys/dev/usb/controller/dwc_otg_atmelarm.c
Commit message (Collapse)AuthorAgeFilesLines
* MFC r266969 and r276717:hselasky2015-02-051-0/+1
| | | | | | Add 64-bit DMA support in the XHCI controller driver. - Fix some comments and whitespaces while at it. - Add support for PAE.
* MFC r265358, r265427, r265777, r265783,hselasky2014-05-231-1/+1
| | | | | | | | | | r265806, r265872, r266012 and r266394: - Multiple DWC OTG host mode related fixes, improvements and optimisations. - Add full support for ISOCHRONOUS transfers to the DWC OTG driver. - Use the interrupt filter to handle basic USB FIFO interrupts. - Fixed unbalanced unlock in case of "dwc_otg_init_fifo()" failure. - Add common spinlock to the USB bus structure.
* Fix for DWC OTG interrupt register programming.hselasky2012-03-051-0/+1
| | | | | | | Fix a compiler warning. Add missing header file. MFC after: 1 week
* Add support for the DesignWare USB 2.0 OTG controller chipset.hselasky2012-01-211-0/+199
Currently the code is not built by any modules. That will be fixed later. The Atmel ARM bus interface file part of this commit is just for sake of example. All registers and bits are declared like macros and not C-structures like in official Synopsis header files. This driver mostly origins from the musb_otg.c driver in FreeBSD except that the chip specific programming has been replaced by the one for DWC 2.0 USB OTG. Some parts related to system suspend and resume have been left like empty functions for the future. USB suspend and resume is fully supported.
OpenPOWER on IntegriCloud