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* MFC r279723, r279724:ian2015-05-231-14/+0
| | | | | | | | | Define new linker set, UART_FDT_CLASS_AND_DEVICE, for registering full (class and device) FDT UART. Define second one, UART_FDT_CLASS, for UART class only. Move the uart_class definitions and fdt compat data into the individual uart implementations, and export them using the new linker-set mechanism.
* MFC r277132: Rename Exynos UART driver functions. No functional change.ian2015-05-231-0/+1
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* MFC r272399, r272602, r274451, r274452:ian2015-05-231-0/+1
| | | | | | | | | | | Add uart driver for Qualcomm MSM 7000/8000 series chips. It is working on IFC6410 board which has Qualcomm Snapdragon SoC. Use documented compat string for msm uart. Make PL011 UART to wait on putc only when TX FIFO is full Make uart_bus_fdt a decendant of ofwbus
* MFC r261083, r261092, r261126, r261127, r261128, r261129, r261130, r261131ian2014-05-141-0/+1
| | | | | | | | | | | | | | Add Atmel serial drivers. uart clock-frequency is a FreeBSD-specific extention. Make it optional and allow the client uart drivers to decide if a frequency is required. Remove redundant declaration for uart devclass. Commit some unrelated, but harmless, FDT ifdefs. Add at91 NAND support, Fix comment. Remove obsolete options and fix comments
* MFC r256839, r256948, r256950, r257299, r257414, r258057, r259090ian2014-05-141-0/+1
| | | | | | | | | | | | | | | Add configuration for the Freescale i.MX53 Quick Start Board. Add the Raspberry Pi BSC (I2C compliant) controller driver. Add Radxa Rock board (by radxa.com) support. Digi-CCWMX53: enable ffec and uart, USB. Add support for Freescale Vybrid Family VF600 Move and rename dwc otg driver to more generic one as it appears to work for rk3188 SoC based board too.
* MFC r257556:ian2013-12-131-0/+5
| | | | | Arrange for uart_cpu_fdt's probe() routine to use the same table of compat strings as uart_bus_fdt's probe().
* Add support for uarts other than the serial console in TI OMAP SoCs.ian2013-08-211-0/+1
| | | | | | | | | The TI uart hardware is ns16550-compatible, except that before it can be used the clocks and power have to be enabled and a non-standard mode control register has to be set to put the device in uart mode (as opposed to irDa or other serial protocols). This adds the extra code in an extension to the standard ns8250 probe routine, and the rest of the driver is just the standard ns8250 code.
* Teach UART to attach Exynos/s3/s5 class driver.ray2013-06-291-0/+1
| | | | | Submitted by: Ruslan Bukin <br@bsdpad.com> Reviewed by: gonzo
* Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.wkoszek2013-04-271-0/+1
| | | | | | Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net> Tested by: wkoszek (ZedBoard) Reviewed by: wkoszek, freebsd-arm@ (no objections raised)
* Integrate Efika MX project back to home.ray2013-03-201-0/+1
| | | | Sponsored by: The FreeBSD Foundation
* Add PrimeCell UART (PL011) drivergonzo2012-08-301-0/+1
| | | | Obtained from: Semihalf
* Merging of projects/armv6, part 8gonzo2012-08-151-0/+1
| | | | | | | | | | | | | | | | | | | | r235162: Initial LPC32x0 support. Includes DTS file for Embedded Artists EA3250 board. Peripherals currently supported: - Serial ports - Interrupt controller - Timers - Ethernet - USB host - Framebuffer (in conjunction with SSD1289 LCD controller) - RTC - SPI - GPIO Submitted by: Jakub Wojciech Klama <jceel@freebsd.org>
* Add sbbc(4), a driver for the BootBus controller found in Serengeti andmarius2010-04-101-0/+1
| | | | | | | | | | StarCat systems which provides time-of-day services for both as well as console service for Serengeti, i.e. Sun Fire V1280. While the latter is described with a device type of serial in the OFW device tree, it isn't actually an UART. Nevertheless the console service is handled by uart(4) as this allowed to re-use quite a bit of MD and MI code. Actually, this idea is stolen from Linux which interfaces the sun4v hypervisor console with the Linux counterpart of uart(4).
* Add the 2nd CCU and PnP devices support on pc98.nyan2008-08-251-0/+4
| | | | | Reviewed by: imp Obtained from: //depot/projects/uart with some fixes
* add device hints to control the rx FIFO interrupt level on 16550A partssam2008-03-121-0/+4
| | | | | | | PR: kern/121421 Submitted by: UEMURA Tetsuya Reviewed by: marcel MFC after: 2 weeks
* Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.raj2008-03-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Don't expose the uart_ops structure directly, but instead havemarcel2007-04-021-0/+9
| | | | | | | | | | | | it obtained through the uart_class structure. This allows us to declare the uart_class structure as weak and as such allows us to reference it even when it's not compiled-in. It also allows is to get the uart_ops structure by name, which makes it possible to implement the dt tag handling in uart_getenv(). The side-effect of all this is that we're using the uart_class structure more consistently which means that we now also have access to the size of the bus space block needed by the hardware when we map the bus space, eliminating any hardcoding.
* Remove definitions of uart_[gs]etdreg. They are not used anymore andmarcel2006-05-231-6/+0
| | | | were in fact wrong.
* Start each of the license/copyright comments with /*-, minor shuffle of linesimp2005-01-061-1/+1
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* Revert the introduction of iobase in struct uart_bas. Both the SAB82532marcel2003-09-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and the Z8530 drivers used the I/O address as a quick and dirty way to determine which channel they operated on, but formalizing this by introducing iobase is not a solution. How for example would a driver know which channel it controls for a multi-channel UART that only has a single I/O range? Instead, add an explicit field, called chan, to struct uart_bas that holds the channel within a device, or 0 otherwise. The chan field is initialized both by the system device probing (i.e. a system console) or it is passed down to uart_bus_probe() by any of the bus front-ends. As such, it impacts all platforms and bus drivers and makes it a rather large commit. Remove the use of iobase in uart_cpu_eqres() for pc98. It is expected that platforms have the capability to compare tag and handle pairs for equality; as to determine whether two pairs access the same device or not. The use of iobase for pc98 makes it impossible to formalize this and turn it into a real newbus function later. This commit reverts uart_cpu_eqres() for pc98 to an unimplemented function. It has to be reimplemented using only the tag and handle fields in struct uart_bas. Rewrite the SAB82532 and Z8530 drivers to use the chan field in struct uart_bas. Remove the IS_CHANNEL_A and IS_CHANNEL_B macros. We don't need to abstract anything anymore. Discussed with: nyan Tested on: i386, ia64, sparc64
* - Keep the base address in struct uart_bas for sab82532 and z8530 modules.nyan2003-09-231-0/+1
| | | | - Remove buggy uart_cpu_busaddr() function.
* The uart(4) driver is an universal driver for various UART hardware.marcel2003-09-061-0/+82
It improves on sio(4) in the following areas: o Fully newbusified to allow for memory mapped I/O. This is a must for ia64 and sparc64, o Machine dependent code to take full advantage of machine and firm- ware specific ways to define serial consoles and/or debug ports. o Hardware abstraction layer to allow the driver to be used with various UARTs, such as the well-known ns8250 family of UARTs, the Siemens sab82532 or the Zilog Z8530. This is especially important for pc98 and sparc64 where it's common to have different UARTs, o The notion of system devices to unkludge low-level consoles and remote gdb ports and provides the mechanics necessary to support the keyboard on sparc64 (which is UART based). o The notion of a kernel interface so that a UART can be tied to something other than the well-known TTY interface. This is needed on sparc64 to present the user with a device and ioctl handling suitable for a keyboard, but also allows us to cleanly hide an UART when used as a debug port. Following is a list of features and bugs/flaws specific to the ns8250 family of UARTs as compared to their support in sio(4): o The uart(4) driver determines the FIFO size and automaticly takes advantages of larger FIFOs and/or additional features. Note that since I don't have sufficient access to 16[679]5x UARTs, hardware flow control has not been enabled. This is almost trivial to do, provided one can test. The downside of this is that broken UARTs are more likely to not work correctly with uart(4). The need for tunables or knobs may be large enough to warrant their creation. o The uart(4) driver does not share the same bumpy history as sio(4) and will therefore not provide the necessary hooks, tweaks, quirks or work-arounds to deal with once common hardware. To that extend, uart(4) supports a subset of the UARTs that sio(4) supports. The question before us is whether the subset is sufficient for current hardware. o There is no support for multiport UARTs in uart(4). The decision behind this is that uart(4) deals with one EIA RS232-C interface. Packaging of multiple interfaces in a single chip or on a single expansion board is beyond the scope of uart(4) and is now mostly left for puc(4) to deal with. Lack of hardware made it impossible to actually implement such a dependency other than is present for the dual channel SAB82532 and Z8350 SCCs. The current list of missing features is: o No configuration capabilities. A set of tunables and sysctls is being worked out. There are likely not going to be any or much compile-time knobs. Such configuration does not fit well with current hardware. o No support for the PPS API. This is partly dependent on the ability to configure uart(4) and partly dependent on having sufficient information to implement it properly. As usual, the manpage is present but lacks the attention the software has gotten.
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