| Commit message (Collapse) | Author | Age | Files | Lines |
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For new eMMC chips, we must signal controller HC capability in OP_COND command.
Detect, report and use 8-bit bus if is available.
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Add defines for SDHCI 3.0 controllers.
Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT.
Save the command-and-flags value into shadow register when it is written.
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Handle the possibility that SDHCI_PLATFORM_START_TRANSFER() can fail.
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Add code to set and reset open-drain mode on the bus when requested.
When command and data interrupts have been aggregated together, don't do
the data-completed processing if a command-error interrupt is also asserted.
Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.
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- Nuke unused sdhci_softc.
- Static'ize sdhci_debug local to sdhci.c.
- Const'ify PCI device description strings.
- Nuke redundant resource ID members from sdhci_pci_softc.
- Nuke unused hw.sdhci_pci.debug tunable.
- Add support for using MSI instead of INTx, controllable via the tunable
hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD
controller.
- Use NULL instead of 0 for pointers.
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Fixes to the ti_sdhci and sdhci drivers (fix clock divisor calcs).
Use the ti_sdhci driver instead of ti_mmchs for Pandaboard.
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r261957, r261983, r261094,
r261955, r261958,
Add a driver to provide access to imx6 on-chip one-time-programmble data.
Make it possible to access the ocotp registers before the ocotp device
is attached, by establishing a temporary mapping of the registers when
necessary.
It turns out Freescale cleverly made the ocotp device compatible across
several different families of SoCs, so move it to the freescale directory
and prefix everything with fsl rather than imx6.
Convert the imx6 sdhci "R1B fix" from a busy-loop in the interrupt handler
to a callout.
Increase the wait time for acquiring the SD bus from 10 to 250ms.
If no compatible cards were found after probing the SD bus, say so.
Add timeout logic to sdhci, separate from the timeouts done by the hardware.
After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA
rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing
any possibility of recovering from the error.
Add a helper routine to depth-search the device tree for a node with a
matching 'compatible' property.
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The sdhci spec says that if the base or timeout clock frequency in the
capabilities register is zero, the driver must obtain the frequency "from
another source." This change defines that other source to be the low-level
hardware driver, which can pre-set the frequencies in slot.max_clk and
slot.timeout_clk before calling sdhci_init_slot().
This helps with a growing number of SoCs that have sdhci base clock
frequencies that either won't fit into the range allowed by the number of
bits available in the capabilities register, or the frequency is runtime-
configurable.
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the response bits the way we do in software. While the hardware is just
doing the sensible thing rather than leaving it to the software, it's in
violation of the spec by doing so. Grrrr.
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has to be recalculated every time the SD clock frequency changes.
Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.
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In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
to start and finish transfer
- platform_will_handle - check whether transaction is
suitable for backend. If not - driver will fall back
to PIO mode.
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by: ian@
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- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
implementation. By re-implementing this method hardware
drivers can control frequency controller operates when
executing initialization sequence
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- Data timeout is broken
- Data timeout uses SD clock
- Capabilities register is unavailable
Add calculations for clock divisor for SDHCI 3.0
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sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.
sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface
No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.
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Submitted by: Daan Vreeken <Daan vitsch.nl>
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some Lenovo laptops.
The conroller needs a quirk to lower its frequency, and after
that it operates normally.
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The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.
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1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression
'*(int *)result = val' to assign to result which is uintptr_t *.
This does not work on big-endian 64 bit systems.
2. The media_size ivar is declared as 'off_t' which does not fit
into uintptr_t in 32bit systems, change this to long.
Submitted by: kanthms at netlogicmicro com (initial version)
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This makes reads 10 times faster.
Discussed with: mav
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Move wakeup() out of the lock.
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Do not issue command if there is no card, clock or power.
Controller will not detect command timeout without clock active.
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To be able to correctly suspend/resume with card inserted,
respective support should be also implemented at mmc and mmcsd layers.
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sdhci supports up to 65535 blocks transfers, at91_mci - one block.
Enable multiblock operations disabled before to follow at91_mci driver
limitations.
Reviewed by: imp@
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Driver supports PCI devices with class 8 and subclass 5 according to
SD Host Controller Specification.
Update NOTES, enable module and static build.
Enable related mmc and mmcsd modules build.
Discussed on: mobile@, current@
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