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path: root/sys/dev/sdhci/sdhci.c
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* MFC r279359, r279360:ian2015-05-231-4/+16
| | | | | | For new eMMC chips, we must signal controller HC capability in OP_COND command. Detect, report and use 8-bit bus if is available.
* MFC r277306, r277307, r277346:ian2015-02-131-1/+2
| | | | | | | | Add defines for SDHCI 3.0 controllers. Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT. Save the command-and-flags value into shadow register when it is written.
* MFC r277027:ian2015-02-131-8/+12
| | | | Handle the possibility that SDHCI_PLATFORM_START_TRANSFER() can fail.
* MFC r275944, r275946, r275949, r275950:ian2014-12-271-11/+33
| | | | | | | | | | | Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit.
* MFC: r270885, r270948marius2014-09-031-15/+3
| | | | | | | | | | | | - Nuke unused sdhci_softc. - Static'ize sdhci_debug local to sdhci.c. - Const'ify PCI device description strings. - Nuke redundant resource ID members from sdhci_pci_softc. - Nuke unused hw.sdhci_pci.debug tunable. - Add support for using MSI instead of INTx, controllable via the tunable hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD controller. - Use NULL instead of 0 for pointers.
* MFC r264096, r264097, r264099 r264100, r264101, r264102, r264119:ian2014-05-271-1/+2
| | | | | | Fixes to the ti_sdhci and sdhci drivers (fix clock divisor calcs). Use the ti_sdhci driver instead of ti_mmchs for Pandaboard.
* MFC r261938, r261939, r261940, r261944, r261945, r261946, r261947, r261956, ↵ian2014-05-151-16/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r261957, r261983, r261094, r261955, r261958, Add a driver to provide access to imx6 on-chip one-time-programmble data. Make it possible to access the ocotp registers before the ocotp device is attached, by establishing a temporary mapping of the registers when necessary. It turns out Freescale cleverly made the ocotp device compatible across several different families of SoCs, so move it to the freescale directory and prefix everything with fsl rather than imx6. Convert the imx6 sdhci "R1B fix" from a busy-loop in the interrupt handler to a callout. Increase the wait time for acquiring the SD bus from 10 to 250ms. If no compatible cards were found after probing the SD bus, say so. Add timeout logic to sdhci, separate from the timeouts done by the hardware. After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing any possibility of recovering from the error. Add a helper routine to depth-search the device tree for a node with a matching 'compatible' property.
* Style changes and typos fixed.rpaulo2013-08-191-8/+13
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* Allow a hardware driver to pass clock frequencies into the sdhci driver.ian2013-08-191-8/+18
| | | | | | | | | | | | | The sdhci spec says that if the base or timeout clock frequency in the capabilities register is zero, the driver must obtain the frequency "from another source." This change defines that other source to be the low-level hardware driver, which can pre-set the frequencies in slot.max_clk and slot.timeout_clk before calling sdhci_init_slot(). This helps with a growing number of SoCs that have sdhci base clock frequencies that either won't fit into the range allowed by the number of bits available in the capabilities register, or the frequency is runtime- configurable.
* Add a new SDHCI_QUIRK_DONT_SHIFT_RESPONSE for hardware that pre-shiftsian2013-08-181-2/+7
| | | | | | the response bits the way we do in software. While the hardware is just doing the sensible thing rather than leaving it to the software, it's in violation of the spec by doing so. Grrrr.
* When the timeout clock is based on the SD clock, the timeout counterian2013-08-161-17/+21
| | | | | | | | | has to be recalculated every time the SD clock frequency changes. Also, tidy up the counter calculation... it makes no sense to calculate a value one larger than the limit, then whine that it's too large and truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't calculate the counter at all, just set it to the limit value.
* Add hooks for plugging platform-provided transfer backend.gonzo2013-02-281-6/+28
| | | | | | | | | | | | | In order to use platorm backend hardware driver should impement three methods: - platform_start_transfer and platform_finish_transfer to start and finish transfer - platform_will_handle - check whether transaction is suitable for backend. If not - driver will fall back to PIO mode. Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Approved by: ian@
* Remove accidentally committed debug panic(9) callgonzo2013-02-171-5/+1
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* Disable debug accidentally enabled by previous commitgonzo2013-02-161-1/+1
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* Various timing-related fixes:gonzo2013-02-161-12/+44
| | | | | | | | | | - Replace divisor numbers with more descirptive names - Properly calculate minimum frequency for SDHCI 3.0 - Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock - Add min_freq method to sdhci_if.m and provide default implementation. By re-implementing this method hardware drivers can control frequency controller operates when executing initialization sequence
* - Get proper maximum clock frequency for SDHCI v3.0 and highergonzo2012-11-301-4/+10
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* Add new quirks:gonzo2012-10-291-14/+47
| | | | | | | | - Data timeout is broken - Data timeout uses SD clock - Capabilities register is unavailable Add calculations for clock divisor for SDHCI 3.0
* Split sdhci driver in two parts: sdhci and sdhci_pci.gonzo2012-10-161-548/+246
| | | | | | | | | | | sdchi encapsulates a generic SD Host Controller logic that relies on actual hardware driver for register access. sdhci_pci implements driver for PCI SDHC controllers using new SDHCI interface No kernel config modifications are required, but if you load sdhc as a module you must switch to sdhci_pci instead.
* Return back double spacing.glebius2012-07-301-1/+1
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* Fix typo in comment, should be MHz here.glebius2012-07-211-1/+1
| | | | Submitted by: Daan Vreeken <Daan vitsch.nl>
* Add support for RICOH R5CE823 card reader, that can be found inglebius2012-02-091-0/+25
| | | | | | | some Lenovo laptops. The conroller needs a quirk to lower its frequency, and after that it operates normally.
* Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.ed2011-11-071-1/+1
| | | | | | The SYSCTL_NODE macro defines a list that stores all child-elements of that node. If there's no SYSCTL_DECL macro anywhere else, there's no reason why it shouldn't be static.
* Fix read_ivar implementation for MMC and SD.jchandra2011-05-301-14/+14
| | | | | | | | | | | 1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression '*(int *)result = val' to assign to result which is uintptr_t *. This does not work on big-endian 64 bit systems. 2. The media_size ivar is declared as 'off_t' which does not fit into uintptr_t in 32bit systems, change this to long. Submitted by: kanthms at netlogicmicro com (initial version)
* Force DMA for controller found in Lenovo T510 (probably in others too).pjd2011-02-271-0/+2
| | | | | | This makes reads 10 times faster. Discussed with: mav
* Add support for interruptless kernel dumping.mav2009-02-171-0/+6
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* Fix read_ivar prototype.imp2009-02-101-1/+1
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* Add hw.sdhci.debug sysctl to control debug level.mav2009-01-281-20/+23
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* Cleanup msleep() arguments.mav2008-12-061-2/+2
| | | | Move wakeup() out of the lock.
* Forget current bus power settings on full reset. Chip must be reconfigured.mav2008-12-061-3/+8
| | | | | Do not issue command if there is no card, clock or power. Controller will not detect command timeout without clock active.
* Add controller suspend/resume support.mav2008-12-011-0/+27
| | | | | To be able to correctly suspend/resume with card inserted, respective support should be also implemented at mmc and mmcsd layers.
* Allow card reader bridge driver to report maximum supported transfer size.mav2008-10-291-0/+4
| | | | | | | | | sdhci supports up to 65535 blocks transfers, at91_mci - one block. Enable multiblock operations disabled before to follow at91_mci driver limitations. Reviewed by: imp@
* Import sdhci (PCI SD Host Controller) driver.mav2008-10-211-0/+1530
Driver supports PCI devices with class 8 and subclass 5 according to SD Host Controller Specification. Update NOTES, enable module and static build. Enable related mmc and mmcsd modules build. Discussed on: mobile@, current@
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