summaryrefslogtreecommitdiffstats
path: root/sys/dev/scc
Commit message (Collapse)AuthorAgeFilesLines
* MFC r260057:dim2014-01-041-15/+2
| | | | | | | In sys/dev/scc, remove unused static function scc_setmreg(). While here, invoke scc_getmreg() in two more places where it can be used. Reviewed by: marcel
* Make r253899 compile.marius2013-08-031-0/+4
|
* Const'ify scc_driver_name.marius2013-08-022-2/+2
|
* - Use NULL instead of 0 for pointers.marius2013-08-024-7/+5
| | | | - Remove unnecessary __RMAN_RESOURCE_VISIBLE.
* - Implement iclear methods for QUICC and SAB 82532. With r253161 in place,marius2013-08-023-24/+41
| | | | | | | | | | | | | | | | | | | | | | | | this is is crucial at least for the latter. What happens is that attaching uart(4) to scc(4) causes the SAB 82532 to "receive" something and trigger a SER_INT_RXREADY interrupt, given that at least fast/filter interrupts are already enabled. Prior to r253161, uart_bus_ihand() was set up at this point and handled that condition, i. e. read the RX FIFO and issued a Receive Message Complete. Now, uart_bus_ihand() and uart_intr() are setup after attaching uart(4), leaving the SER_INT_RXREADY interrupt triggered during the latter to be handled by the iclear method. However, with that method not implement, this in turn causes SAB 82532 to not issue any further SER_INT_RXREADY interrupts until the RX FIFO is full again. Thus, 15 received bytes go to nowhere, given that "the other half" of the RX FIFO is used for status information. Hence, implementing sab82532_bfe_iclear() fixes things again. Potentially, the same problem exists for QUICC. - Remove unnecessary __RMAN_RESOURCE_VISIBLE. - Remove a superfluous header. - Use KOBJMETHOD_END. - Mark unused arguments as such. - Remove variables unused after initialization. Reviewed by: marcel (earlier version)
* - There's no need to overwrite the default device method with the defaultmarius2011-11-224-12/+8
| | | | | | | | | | one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
* Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.ed2011-11-071-1/+1
| | | | This means that their use is restricted to a single C file.
* Recognize the SAB 82532 found in Fujitsu PRIMEPOWER650 and 900.marius2011-05-151-1/+2
|
* Make iclear return int, since that matches all function definitions of it.imp2009-02-051-1/+1
|
* With rev 1.24 of sys/powerpc/powermac/macio.c, we now get amarcel2008-04-266-7/+44
| | | | | | | | | | | | | | total of 6 interrupt resources for scc(4) on macio(4). This is 3 per channel, of which the 1st of each channel is the interrupt associated with the SCC. The other 2 are for DMA operation. Change scc_bfe_attach() to accept an argument that's the number of interrupts per channel (ipc) and change each bus front-end (bfe) to pass that argument through a wrapper for the device_attach method. For now, we only allocate the 1st interrupt of each channel to perserve behaviour.
* Support for Freescale QUad Integrated Communications Controller.raj2008-03-034-0/+248
| | | | | | | | | | | | | The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500
* Add method enabled() to the SCC interface. This method can be usedmarcel2007-03-283-0/+22
| | | | | | | | by driver backends to mark individual channels as enabled or not. The default implementation of this method always mark channels as enabled. This method is currently not used, but is added with the PowerQUICC in mind where the 2nd SCC channel can be disabled.
* Allow the range of a SCC class to be 0. This gives all childmarcel2007-03-281-5/+7
| | | | | | devices the same (overlapping) I/O range. This is useful for embedded communications controllers like the CPM of various models of the PowerQUICC.
* Pass the RID from the bus frontends to the core probe function.marcel2007-03-225-7/+7
| | | | | | Currently all RIDs are 0, but for PCI devices this typically isn't the case. This change is made with future PCI support in mind.
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-232-13/+15
| | | | | | | | | | | | | bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
* Fix braino: The cl_range field should not hold the shifted I/Omarcel2006-07-262-3/+3
| | | | | | | space range per channel, but rather the unshifted range. The shifting depends on the bus. The hardcoded shift was specific to the SBus on sparc64. The shifted range is now determined at run-time. This fixes the mac-io attachment.
* Revert previous commit. Spinlocks hold interrupts disabled, somarcel2006-07-251-13/+11
| | | | | | preemption is not possible. Pointed out by: jhb@
* If we have multiple interrupt resources, like for Z8530 clones on themarcel2006-07-241-11/+13
| | | | | | | | | | mac-io bus, we cannot setup FAST interrupt handlers. This because we use spinlocks to protect the hardware and all interrupt resources are assigned the same interrupt handler. When the interrupt handler is invoked for interrupt X, it could be preempted for interrupt Y while it was holding the lock (where X and Y are the interrupt resources corresponding a single instance of this driver). This is a deadlock. By only using a MPSAFE handler in that case we prevent preemption.
* The Z8530 on the MacIO has an interrupt per channel. Deal with thismarcel2006-04-042-32/+57
| | | | | by having interrupt resource variables per channel. We don't set up different interrupt handlers per channel, though.
* Add a MacIO bus attachment. The Z8530 as present in the Mac needsmarcel2006-04-017-18/+101
| | | | | | | | a different register shift and is fed by a different clock than we use for UltraSPARC hardware. To deal with this, the regshft and rclk fields in the class structure are removed and bus frontends now pass the right regshft and rclk to the probe function where they're put in the BAS and passed in to subordinate drivers.
* Fix cut-n-paste braino in previous commit: s/puc/scc/gmarcel2006-03-311-1/+1
| | | | Pointy hat: marcel@
* Add a DRIVER_MODULE declaration for fhc(4) as this attachement ismarcel2006-03-311-0/+1
| | | | | | also used for the FHC bus. Pointed out by: marius@
* Add scc(4), a driver for serial communications controllers. Thesemarcel2006-03-308-0/+1333
controllers typically have multiple channels and support a number of serial communications protocols. The scc(4) driver is itself an umbrella driver that delegates the control over each channel and mode to a subordinate driver (like uart(4)). The scc(4) driver supports the Siemens SAB 82532 and the Zilog Z8530 and replaces puc(4) for these devices.
OpenPOWER on IntegriCloud