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* With rev 1.24 of sys/powerpc/powermac/macio.c, we now get amarcel2008-04-261-2/+11
| | | | | | | | | | | | | | total of 6 interrupt resources for scc(4) on macio(4). This is 3 per channel, of which the 1st of each channel is the interrupt associated with the SCC. The other 2 are for DMA operation. Change scc_bfe_attach() to accept an argument that's the number of interrupts per channel (ipc) and change each bus front-end (bfe) to pass that argument through a wrapper for the device_attach method. For now, we only allocate the 1st interrupt of each channel to perserve behaviour.
* Add method enabled() to the SCC interface. This method can be usedmarcel2007-03-281-0/+5
| | | | | | | | by driver backends to mark individual channels as enabled or not. The default implementation of this method always mark channels as enabled. This method is currently not used, but is added with the PowerQUICC in mind where the 2nd SCC channel can be disabled.
* Allow the range of a SCC class to be 0. This gives all childmarcel2007-03-281-5/+7
| | | | | | devices the same (overlapping) I/O range. This is useful for embedded communications controllers like the CPM of various models of the PowerQUICC.
* Pass the RID from the bus frontends to the core probe function.marcel2007-03-221-3/+3
| | | | | | Currently all RIDs are 0, but for PCI devices this typically isn't the case. This change is made with future PCI support in mind.
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-11/+13
| | | | | | | | | | | | | bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
* Fix braino: The cl_range field should not hold the shifted I/Omarcel2006-07-261-2/+2
| | | | | | | space range per channel, but rather the unshifted range. The shifting depends on the bus. The hardcoded shift was specific to the SBus on sparc64. The shifted range is now determined at run-time. This fixes the mac-io attachment.
* Revert previous commit. Spinlocks hold interrupts disabled, somarcel2006-07-251-13/+11
| | | | | | preemption is not possible. Pointed out by: jhb@
* If we have multiple interrupt resources, like for Z8530 clones on themarcel2006-07-241-11/+13
| | | | | | | | | | mac-io bus, we cannot setup FAST interrupt handlers. This because we use spinlocks to protect the hardware and all interrupt resources are assigned the same interrupt handler. When the interrupt handler is invoked for interrupt X, it could be preempted for interrupt Y while it was holding the lock (where X and Y are the interrupt resources corresponding a single instance of this driver). This is a deadlock. By only using a MPSAFE handler in that case we prevent preemption.
* The Z8530 on the MacIO has an interrupt per channel. Deal with thismarcel2006-04-041-29/+53
| | | | | by having interrupt resource variables per channel. We don't set up different interrupt handlers per channel, though.
* Add a MacIO bus attachment. The Z8530 as present in the Mac needsmarcel2006-04-011-5/+5
| | | | | | | | a different register shift and is fed by a different clock than we use for UltraSPARC hardware. To deal with this, the regshft and rclk fields in the class structure are removed and bus frontends now pass the right regshft and rclk to the probe function where they're put in the BAS and passed in to subordinate drivers.
* Add scc(4), a driver for serial communications controllers. Thesemarcel2006-03-301-0/+542
controllers typically have multiple channels and support a number of serial communications protocols. The scc(4) driver is itself an umbrella driver that delegates the control over each channel and mode to a subordinate driver (like uart(4)). The scc(4) driver supports the Siemens SAB 82532 and the Zilog Z8530 and replaces puc(4) for these devices.
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