| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | With rev 1.24 of sys/powerpc/powermac/macio.c, we now get a | marcel | 2008-04-26 | 1 | -1/+8 |
| | | | | | | | | | | | | | | | total of 6 interrupt resources for scc(4) on macio(4). This is 3 per channel, of which the 1st of each channel is the interrupt associated with the SCC. The other 2 are for DMA operation. Change scc_bfe_attach() to accept an argument that's the number of interrupts per channel (ipc) and change each bus front-end (bfe) to pass that argument through a wrapper for the device_attach method. For now, we only allocate the 1st interrupt of each channel to perserve behaviour. | ||||
| * | Support for Freescale QUad Integrated Communications Controller. | raj | 2008-03-03 | 1 | -0/+95 |
| The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500 | |||||
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| Raptor Engineering's fork of pfsense FreeBSD src with pfSense changes | Raptor Engineering, LLC |
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