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* Allocating 2 MSI messages do not seem to work on certain controllersyongari2009-02-111-1/+2
| | | | | | | so use just 1 MSI message. This fixes regression introduced in r188381. Tested by: many
* Reclaim transmitted frames in re_tick(). This is for PCIeyongari2009-02-091-1/+8
| | | | | | controllers that lose Tx completion interrupts under certain conditions. With this change it's safe to use MSI on PCIe controllers so enable MSI on these controllers.
* - Add support for 8110SCe part. Some magic registers were taken fromjkim2009-01-201-19/+39
| | | | | | | Linux driver. - Swap hardware revisions for 8110S and 8169S as Linux driver claims. Reviewed by: yongari (early version)
* Retire RL_FLAG_INVMAR bit to match its comment and reality.jkim2009-01-201-11/+9
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* - Do not read and write RX configuration register multiple times.jkim2009-01-201-66/+31
| | | | | | | | | - Always program RX configuration register from scratch instead of doing read/modify/write. - Rename re_setmulti() to re_set_rxmode() to be reflect reality. - Simplify hash filter logic a little while I am here. Reviewed by: yongari (early version)
* Sometimes RTL8168B seems to take long time to access GMII registersyongari2009-01-191-4/+4
| | | | | | | | in device attach phase. Double GMII register access timeout value to fix the issue. Reported by: wkoszek Tested by: wkoszek
* Since we don't request reset for rlphy(4), the link state 'UP'yongari2008-12-221-0/+2
| | | | | | | | | | event from mii(4) may not be delivered if valid link was already established. To address the issue, check current link state after driving MII_TICK. This should fix a regression introduced in r185753 on fast ethernet controllers. Reported by: csjp, Bruce Cran < bruce <> cran DOT org DOT uk > Tested by: csjp, Bruce Cran (initial version)
* It seems that RealTek PCIe controllers require an explicit Tx pollyongari2008-12-171-10/+15
| | | | | | | | | | | | | | | | | | | command whenever Tx completion interrupt is raised. The Tx poll bit is cleared when all packets waiting to be transferred have been processed. This means the second Tx poll command can be silently ignored as the Tx poll bit could be still active while processing of previous Tx poll command is in progress. To address the issue re(4) used to invoke the Tx poll command in Tx completion handler whenever it detects there are pending packets in TxQ. However that still does not seem to completely eliminate watchdog timeouts seen on RealTek PCIe controllers. To fix the issue kick Tx poll command only after Tx completion interrupt is raised as this would indicate Tx is now idle state such that it can accept new Tx poll command again. While here apply this workaround for PCIe based controllers as other controllers does not seem to have this limitation. Tested by: Victor Balada Diaz < victor <> bsdes DOT net >
* For RTL8168C SPIN2 controllers, make sure to take the controlleryongari2008-12-171-1/+28
| | | | | | | | out of sleep mode prior to accessing to PHY. This should fix device attach failure seen on these controllers. Also enable the sleep mode when device is put into sleep state. PR: kern/123123, kern/123053
* Make WOL work on RTL8168B. This controller seems to requireyongari2008-12-111-0/+5
| | | | | | explicit command to enable Rx MAC prior to entering D3. Tested by: Cyrus Rahman <crahman <> gmail DOT com>
* Don't access undocumented register 0x82 on controllers thatyongari2008-12-111-2/+14
| | | | | | | have no such register. While here clear undocumented PHY register 0x0B for RTL8110S. Obtained from: RealTek FreeBSD driver
* Newer RealTek controllers requires setting stop request bit toyongari2008-12-111-3/+9
| | | | terminate active Tx/Rx operation.
* Always put controller into known state before device intialization.yongari2008-12-111-7/+5
| | | | | While here remove re_reset calls invoked in system error case as controller reset is always done in device initialization.
* Partly revert r185756. RTL8169SC doesn't like reduced delays inyongari2008-12-111-2/+2
| | | | | | | | GMII access while Tx/Rx is in progress. Reported by: Jaakko Heinonen <jh <> saunalahti DOT fi>, Anton Yuzhaninov <citrin <> citrin DOT ru> Tested by: Jaakko Heinonen <jh <> saunalahti DOT fi>
* Reduce spin wait time consumed in GMII register access routines.yongari2008-12-081-4/+2
| | | | | | | | Waiting for 1ms for each GMII register access looks overkill and it may also decrease overall performance of driver because re(4) invokes mii_tick for every hz. Tested by: rpaulo
* o Implemented miibus_statchg handler. It detects whether re(4)yongari2008-12-081-28/+51
| | | | | | | | | | | | | | | | established a valid link or not. In miibus_statchg handler add a check for established link is valid one for the controller(e.g. 1000baseT is not a valid link for fastethernet controllers.) o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers. o Added additional check to know whether we've really encountered watchdog timeouts or missed Tx completion interrupts. This change may help to track down the cause of watchdog timeouts. o In interrupt handler, removed a check for link state change interrupt. Not all controllers have the bit and re(4) did not rely on the event for a long time. In addition, re(4) didn't request the interrupt in RL_IMR register. Tested by: rpaulo
* Make sure to return the result of meida change request.yongari2008-12-081-2/+3
| | | | Previously it used to return success regardless of the result.
* Add 8168D support.yongari2008-12-021-1/+3
| | | | Submitted by: Andrew < andrewwtulloch <> gmail DOT com >
* Read ethernet address from ID registers for RTL8102E/RTL8102EL asyongari2008-09-061-1/+2
| | | | | | | reading from EEPROM doesn't seem to work on these controllers. Reported by: Milan Obuch ( freebsd-net at dino dot sk ) Tested by: Milan Obuch ( freebsd-net at dino dot sk )
* Fix VLAN hardware tag insertion/stripping on big-endianyongari2008-08-131-2/+2
| | | | | | | | architectures. Reported by: naddy Tested on: sparc64 MFC after: 1 week
* Rearrange conditional compilation directives. This makes syntaxyongari2008-08-041-2/+3
| | | | highlighting work in vim.
* Remove return keyword at the end of functions that return void.yongari2008-08-041-14/+0
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* Remove register keyword.yongari2008-08-041-4/+4
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* Use ANSI C declarations for all functions.yongari2008-08-041-104/+41
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* Don't enable TSO by default. Users of RTL8169/8110 reportedyongari2008-08-041-0/+7
| | | | | | | | | | | | watchdog timeout issues and the root cause seems to stem from silicon bug of controller. Personally I couldn't reproduce it on RTL8169 controller but it seems it's dependent on usage pattern. For newer PCIe based controllers I have no TSO complaints but turning off TSO would be more safe. Users who are sure that their controller works with TSO can still reenable the TSO with ifconfig(8). Reported by: Oliver Lehmann (lehmann at ans-netz dot de), Eugene Butusov (ebutusov at gmail dot com)
* The number of bits reserved for MSS in RealTek controllers isyongari2008-08-041-0/+18
| | | | | | | 11bits. This limits the maximum interface MTU size in TSO case as upper stack should not generate TCP segments with MSS greater than the limit. Armed with this information, disable TSO if interface MTU is greater than the limit.
* Add driver support for RTL8102E and RTL8102EL which is the secondyongari2008-07-091-1/+8
| | | | | | | | | generation of RTL810x PCIe fast ethernet controller. Note, Tx/Rx descriptor format is different from that of first generation of RTL8101E series. Jumbo frame is not supported for RTL810x family. Tested by: NAGATA Shinya ( maya AT negeta DOT com )
* Disable jumbo frame support for RTL810x fast ethernet controllers.yongari2008-07-091-1/+2
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* Add a new RTL8169 variant, 8169SB(L)/8110SB(L).yongari2008-07-021-1/+3
| | | | | Reported by: nork Tested by: nork
* Add basic support for RTL8168C, RTL8168CP, RTL8111C and RTL8111CP.yongari2008-07-021-43/+134
| | | | | | | | | | | | | | | | ATM Tx/Rx checksum offload is supported but TSO and jumbo frame is not yet supported. Because these newer controllers use different descriptor formats, a flag RL_FLAG_DESCV2 flag was introduced to handle that case in Tx/Rx handler. Also newer controllers seems to require to not touch 'enable Tx/Rx bit' in RL_CPLUS_CMD register so don't blindly try to set that bits. Note, it seems that there is still power-saving related issue where driver fails to attach PHY. Rebooting seems to fix that issue but number of required reboots varys. Many thanks to users that helped during developement. I really appreciate their patient and test/feedbacks.
* Display detected chip revision in device attach. This will help toyongari2008-07-021-2/+5
| | | | | diagnose revision specific issues in future. Also add 0x to notify that the revision number is in hex form.
* If MSI is not active make sure to disable MSI in EEPROM.yongari2008-07-021-0/+11
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* In device detach don't access ifnet structure unless device isyongari2008-07-021-4/+4
| | | | | attached. This fixes NULL pointer dereference when polling(9) is active and unsupported hardware is detected in device attach.
* Toggling IFF_ALLMULTI flag does not require full interfaceyongari2008-07-021-1/+1
| | | | reintialization.
* Instead of allocating variables for each events/hardware flags, useyongari2008-07-021-47/+41
| | | | | | | | | a dedicated flag that represents controller capabilities/events. This will simplify many part of code that requires different workaround for each controller revisions and will enhance readability. While I'm here move PHY wakeup code up before mii_phy_probe() which seems to help to wake PHY in some cases.
* Switch to memory space register mapping over IO space. If thatyongari2008-07-021-21/+21
| | | | mapping fails fall back to traditional IO space access.
* While accessing EEPROM command register use pre-defined constantyongari2008-07-021-3/+3
| | | | instead of hardcoded value.
* After the change of r176757 re(4) no longer relys on readingyongari2008-07-021-32/+18
| | | | | | | | RL_TXCFG register to identify a device in device probe. Reflect the fact by modifing device description with general ethernet controller family. Note, rl_basetype in struct rl_type is not used and the more detailed information is provided with rl_hwrev structure.
* Remove duplicated H/W revision check.yongari2008-07-021-5/+0
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* Don't touch MSI enable bit in RL_CFG2 register. For unknown reasonyongari2008-04-151-12/+6
| | | | | | | | clearing MSI enable bit for MSI capable hardwares resulted in Tx problems. MSI enable bit is set only when MSI is requested from user. Tested by: remko
* Padding more bytes than necessary one broke another variants ofyongari2008-03-311-1/+1
| | | | | | | | PCIe RealTek chips. Only pad IP packets if the payload is less than 28 bytes. Obtained from: NetBSD PR: kern/122221
* In revision 1.70, 1.71 and 1.84 re(4) tried to workaround checksumyongari2008-03-281-12/+14
| | | | | | | | | | | | | | | | | | offload bugs by manual padding for short IP/UDP frames. Unfortunately it seems that these workaround does not work reliably on newer PCIe variants of RealTek chips. To workaround the hardware bug, always pad short frames if Tx IP checksum offload is requested. It seems that the hardware has a bug in IP checksum offload handling. NetBSD manually pads short frames only when the length of IP frame is less than 28 bytes but I chose 60 bytes to safety. Also unconditionally set IP checksum offload bit in Tx descriptor if any TCP or UDP checksum offload is requested. This is the same way as Linux does but it's not mentioned in data sheet. Obtained from: NetBSD Tested by: remko, danger
* MSI handling on some RealTek chips are broken so disable it byyongari2008-03-231-1/+1
| | | | | | | default. Reported by: Giulio Ferro ( auryn AT zirakzigil DOT org ) Tested by: Giulio Ferro ( auryn AT zirakzigil DOT org )
* For MSI capable hardwares, enable MSI enable bit in RL_CFG2yongari2008-03-231-0/+13
| | | | | register. If MSI was disabled by hw.re.msi_disable tunable expliclty clear the MSI enable bit.
* Some RealTek chips are known to be buggy on DAC handling, soyongari2008-03-231-1/+6
| | | | disable DAC by default.
* VLAN hardware tag information should be set for all desciptors of ayongari2008-03-231-11/+13
| | | | | | | | | multi-descriptor transmission attempt. Datasheet said nothing about this requirements. This should fix a long-standing VLAN hardware tagging issues with re(4). Reported by: Giulio Ferro ( auryn AT zirakzigil DOT org ) Tested by: Giulio Ferro ( auryn AT zirakzigil DOT org )
* Always honor configured VLAN/checksum offload capabilities.yongari2008-03-231-3/+8
| | | | | | Previously re(4) used to blindly enable VLAN hardware tag stripping and Rx checksum offload regardless of enabled optional features of interface.
* Don't map memory/IO resource in device probe and just use PCIyongari2008-03-031-42/+33
| | | | | | vendor/revision/sub device id of the hardware to probe it. This is the same way as NetBSD does and it enhances readabilty a lot.
* Don't allow jumbo frame on 8139C+ controller.yongari2008-03-031-3/+11
| | | | While I'm here add a check for minimal MTU length.
* Implement WOL.yongari2008-03-031-0/+108
| | | | Tested by: Fabian Keil ( freebsd-listen AT fabienkeli DOT de )
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