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* Add message when nvd disks are attached and detached.jimharris2013-07-191-8/+29
| | | | | | | | | | | | As part of this commit, add an nvme_strvis() function which borrows heavily from cam_strvis(). This will allow stripping of leading/trailing whitespace and also handle unprintable characters in model/serial numbers. This function goes into a new nvme_util.c file which is used by both the driver and nvmecontrol. Sponsored by: Intel Reviewed by: carl MFC after: 3 days
* Do not call disk_create() until we have completed all initialization of ourjimharris2013-07-191-2/+2
| | | | | | | | internal disk structure. Sponsored by: Intel Reviewed by: carl MFC after: 3 days
* Define constants for the lengths of the serial number, model numberjimharris2013-07-171-2/+6
| | | | | | | | | | | and firmware revision in the controller's identify structure. Also modify consumers of these fields to ensure they only use the specified number of bytes for their respective fields. Sponsored by: Intel Reviewed by: carl MFC after: 3 days
* Update copyright dates.jimharris2013-07-091-1/+1
| | | | MFC after: 3 days
* Add unmapped bio support to nvme(4) and nvd(4).jimharris2013-04-011-0/+5
| | | | Sponsored by: Intel
* Change a number of malloc(9) calls to use M_WAITOK instead ofjimharris2013-03-261-2/+2
| | | | | | | | M_NOWAIT. Sponsored by: Intel Suggested by: carl Reviewed by: carl
* Add the ability to internally mark a controller as failed, if it is unable tojimharris2013-03-261-1/+21
| | | | | | | | | | | | | | | start or reset. Also add a notifier for NVMe consumers for controller fail conditions and plumb this notifier for nvd(4) to destroy the associated GEOM disks when a failure occurs. This requires a bit of work to cover the races when a consumer is sending I/O requests to a controller that is transitioning to the failed state. To help cover this condition, add a task to defer completion of I/Os submitted to a failed controller, so that the consumer will still always receive its completions in a different context than the submission. Sponsored by: Intel Reviewed by: carl
* Have nvd(4) register for controller notifications.jimharris2013-03-261-17/+54
| | | | | | | Also have nvd maintain controller/namespace relationships internally. Sponsored by: Intel Reviewed by: carl
* Create struct nvme_status.jimharris2013-03-261-2/+2
| | | | | | | | | | | | | | NVMe error log entries include status, so breaking this out into its own data structure allows it to be included in both the nvme_completion data structure as well as error log entry data structures. While here, expose nvme_completion_is_error(), and change all of the places that were explicitly looking at sc/sct bits to use this macro instead. Sponsored by: Intel Reviewed by: carl
* Add an interface for nvme shim drivers (i.e. nvd) to register forjimharris2013-03-261-4/+6
| | | | | | notifications when new nvme controllers are added to the system. Sponsored by: Intel
* Add ability to queue nvme_request objects if no nvme_trackers are available.jimharris2012-10-181-19/+3
| | | | | | | | | This eliminates the need to manage queue depth at the nvd(4) level for Chatham prototype board workarounds, and also adds the ability to accept a number of requests on a single qpair that is much larger than the number of trackers allocated. Sponsored by: Intel
* Add return codes to all functions used for submitting commands to I/Ojimharris2012-10-181-1/+13
| | | | | | queues. Sponsored by: Intel
* Revert previous commit...kevlo2012-10-101-1/+1
| | | | Pointyhat to: kevlo (myself)
* Prefer NULL over 0 for pointerskevlo2012-10-091-1/+1
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* This is the first of several commits which will add NVM Express (NVMe)jimharris2012-09-171-0/+318
support to FreeBSD. A full description of the overall functionality being added is below. nvmexpress.org defines NVM Express as "an optimized register interface, command set and feature set fo PCI Express (PCIe)-based Solid-State Drives (SSDs)." This commit adds nvme(4) and nvd(4) driver source code and Makefiles to the tree. Full NVMe functionality description: Add nvme(4) and nvd(4) drivers and nvmecontrol(8) for NVM Express (NVMe) device support. There will continue to be ongoing work on NVM Express support, but there is more than enough to allow for evaluation of pre-production NVM Express devices as well as soliciting feedback. Questions and feedback are welcome. nvme(4) implements NVMe hardware abstraction and is a provider of NVMe namespaces. The closest equivalent of an NVMe namespace is a SCSI LUN. nvd(4) is an NVMe consumer, surfacing NVMe namespaces as GEOM disks. nvmecontrol(8) is used for NVMe configuration and management. The following are currently supported: nvme(4) - full mandatory NVM command set support - per-CPU IO queues (enabled by default but configurable) - per-queue sysctls for statistics and full command/completion queue dumps for debugging - registration API for NVMe namespace consumers - I/O error handling (except for timeoutsee below) - compilation switches for support back to stable-7 nvd(4) - BIO_DELETE and BIO_FLUSH (if supported by controller) - proper BIO_ORDERED handling nvmecontrol(8) - devlist: list NVMe controllers and their namespaces - identify: display controller or namespace identify data in human-readable or hex format - perftest: quick and dirty performance test to measure raw performance of NVMe device without userspace/physio/GEOM overhead The following are still work in progress and will be completed over the next 3-6 months in rough priority order: - complete man pages - firmware download and activation - asynchronous error requests - command timeout error handling - controller resets - nvmecontrol(8) log page retrieval This has been primarily tested on amd64, with light testing on i386. I would be happy to provide assistance to anyone interested in porting this to other architectures, but am not currently planning to do this work myself. Big-endian and dmamap sync for command/completion queues are the main areas that would need to be addressed. The nvme(4) driver currently has references to Chatham, which is an Intel-developed prototype board which is not fully spec compliant. These references will all be removed over time. Sponsored by: Intel Contributions from: Joe Golio/EMC <joseph dot golio at emc dot com>
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