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* MFC r311935: Pretend we support some IOCTLs to not scary upper layers.mav2017-01-251-0/+5
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* MFC r303554, r303561:mav2016-08-181-0/+19
| | | | Block MSIX negotiation until SMP started and IRQ reshuffled.
* MFC r303553: Make MAC address generation more random.mav2016-08-181-2/+1
| | | | 'ticks' approach does not work at boot time.
* MFC r303551: Fix infinite loops introduced at r303429.mav2016-08-181-2/+2
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* MFC r303514: Fix NTBT_QP_LINKS negotiation.mav2016-08-181-29/+18
| | | | | | | | I believe it never worked correctly for more the one queue even in Linux. This fixes case when one of consumer drivers is not loaded on one side, but its queues still announced as ready if something else brought link up. While there, remove some pointless NULL checks.
* MFC r303510: Clear scratchpad after MSIX negotiation to not leak garbage.mav2016-08-181-0/+1
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* MFC r303494: Once more refactor KPI between ntb_transport(4) and if_ntb(4).mav2016-08-183-87/+139
| | | | | | New design allows to attach multiple consumers to ntb_transport(4) instance. Previous design obtained from Linux theoretically allowed that, but was not practically usable (Linux also has only one consumer driver now).
* MFC r303429, r303437:mav2016-08-185-749/+1152
| | | | | | | | | | | | | Once more refactor KPI between NTB hardware and consumers. New design allows hardware resources to be split between several consumers. For example, one BAR can be dedicated for remote memory access, while other resources can be used for packet transport for virtual Ethernet interface. And even without resource split, this code allows to specify which consumer driver should attach the hardware. From some points this makes the code even closer to Linux one, even though Linux does not provide the described flexibility.
* MFC r303266: Postpone ntb_get_msix_info() till we need to negotiate MSIX.mav2016-08-181-2/+1
| | | | | | | | Calling it earlier increases the window when MSIX info may change. This change does not solve the problem completely, but seems logical. Complete solution should probably include link reset in case of MSIX remap to trigger new negotiation, but we have no way to get notified about that now.
* MFC r302622 (by sephe): ntb: Fix LINTmav2016-08-182-3/+1
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* MFC r302531: Revert odd change, setting limit registers before base.mav2016-08-181-12/+8
| | | | | | | | | | I don't know what errata is mentioned there, I was unable to find it, but setting limit before the base simply does not work at all. According to specification attempt to set limit out of the present window range resets it to zero, effectively disabling it. And that is what I see in practice. Fixing this properly disables access for remote side to our memory until respective xlat is negotiated and set. As I see, Linux does the same.
* MFC r302529: Remove callout_reset(link_work) from ntb_transport_attach().mav2016-08-181-1/+0
| | | | | | At that point link is quite likely not established yet, so messing with scratch registers is premature there. Original commit message mentioned code diff reduction from Linux, but this line is not present in Linux now.
* MFC r302530: Fix wrong copy/paste in r302510.mav2016-08-181-1/+1
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* MFC r302510:mav2016-08-181-29/+10
| | | | | | Simplify MSIX MW BAR xlat setup, and don't forget to unlock its limit. The last fixes SB01BASE_LOCKUP workaround after driver reload.
* MFC r302508: Disable SB01BASE_LOCKUP workaround when split BARs disabled.mav2016-08-181-1/+11
| | | | | | | For some reason hack with sending MSI-X interrupts by writing to remote LAPIC memory works only for 32-bit BARs, that are available only if split BARs mode is enabled in BIOS. If it is not, complain loudly and fall back to less efficient workaround.
* MFC r302499: Improve checksum "offload" support.mav2016-08-181-4/+50
| | | | | | | | | | For compatibility reasons make driver not report any checksum offload by default, since there is indeed none. But if administrator knows that interface is used only for local traffic, he can enable fake checksum offload manually on both sides to save some CPU cycles, since the data are already protected by CRC32 of PCIe link. Sponsored by: iXsystems, Inc.
* MFC r302496: Rewrite if_ntb to use modern interface KPIs and features.mav2016-08-181-90/+249
| | | | | | It includes: link state, if_transmit, buf_ring, multiple queues, bpf, etc. Sponsored by: iXsystems, Inc.
* MFC r302495: Improve memory allocation errors handling on receive.mav2016-08-182-1/+8
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* MFC r302494: Synchronize MTU code with Linux.mav2016-08-182-7/+4
| | | | It is mandatory for transport compatibility.
* MFC r302493: Reimplement doorbell register emulation for NTB_SB01BASE_LOCKUP.mav2016-08-182-61/+50
| | | | | | | This allows at least first three doorbells to work very close to normal hardware, properly signaling events to upper layers without spurious or lost events. Doorbells above the first three may still report spurious events due to lack of reliable information, but they are rarely used.
* MFC r302492: Bring some more order into link and qp state handling.mav2016-08-181-9/+4
| | | | | Do not touch scratchpad registers until link is reported up. Mask and do not handle doorbell events until respective qp is up.
* MFC r302491: Switch ctx_lock from mutex to rmlock.mav2016-08-181-17/+15
| | | | | | | It is odd idea to serialize different MSI-X vectors. Use of rmlocks here allows them to execute in parallel, but still protects ctx. If upper layers require any additional serialization -- they can do it by themselves.
* MFC r302490: Create separate RX taskqueue for each qp.mav2016-08-181-27/+20
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* MFC r302489: Remove rx_completion_task taskqueue.mav2016-08-181-8/+4
| | | | It is not needed after RX lock removed in previous commit.
* MFC r302488: Remove unneeded RX lock, and make TX lock per-qp.mav2016-08-181-11/+7
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* MFC r302487: Reduce code divergence from Linux, preparing for DMA support.mav2016-08-181-59/+73
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* MFC r302486: Fix operation with multiple qps.mav2016-08-181-5/+5
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* MFC r302484: NewBus'ify NTB subsystem.mav2016-08-189-1996/+2458
| | | | | | | | | This follows NTB subsystem modularization in Linux, tuning it to FreeBSD native NewBus interfaces. This change allows to support different types of hardware with different drivers, support multiple NTB instances in a system, ntb_transport module use for needs other then if_ntb, etc. Sponsored by: iXsystems, Inc.
* MFC r302483: Remove some dead code found by Clang static analyzer.mav2016-08-181-18/+4
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* MFC r302482: Fix NTB_SDOORBELL_LOCKUP workaround.mav2016-08-181-2/+6
| | | | | | Since SBARxSZ register can be write-once, it can be unusable for disabling the SBAR. For such case also set SBARxBASE to zero to not intersect with config BAR.
* Fix if_ntb interface setup to include IFF_MULTICAST.vangyzen2016-06-181-1/+1
| | | | | | | | | | | | | This allows IPv6 link local addresses (and other IPv6 functionality) to work. PR: 210355 Submitted by: Steve Wahl and David Bright (both at Dell Inc.) Reviewed by: cem, mav Tested by: mav (on Intel hardware) Approved by: re (kib) MFC after: 5 days Sponsored by: Dell Inc. Differential Revision: https://reviews.freebsd.org/D6885
* When negotiating NTB_SB01BASE_LOCKUP workaround, don't try to limit themav2016-06-041-42/+15
| | | | | | | | | | | | BAR size to 1MB. According to Xeon v3 specifications and my tests, that size register is write-once and so not writeable after BIOS written it. Instead of that, make the code work with BAR of any sufficient size, properly calculating offset within its base. It also simplifies the code. Discussed with: cem MFC after: 2 weeks Sponsored by: iXsystems, Inc.
* When negotiating MSIX parameters, give other head time to see ourmav2016-06-041-3/+10
| | | | | | | | | NTB_MSIX_RECEIVED status, before making upper layers overwrite it. This is not completely perfect, but now it works better then before. MFC after: 2 weeks Sponsored by: iXsystems, Inc.
* Re-enable write combining, disabled by default at r295486.mav2016-05-241-0/+4
| | | | | | | if_ntb(4) strongly benefits from WC, improving throughput from 350Mbit/s to 8-10Gbit/s on my tests. MFC after: 1 week
* ntb_hw(4): Only record the first three MSIX vectorscem2016-05-231-4/+14
| | | | | | | | | Don't overrun the msix_data array by reading the (unused) link state interrupt information. Reported by: mav (earlier version) Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D6489
* ntb_hw(4): Add sysctls for administrative/test link config, statecem2016-05-182-11/+89
| | | | | | | | | dev.ntb_hw.0.admin_up=0/1: Like ifconfig UP/DOWN. dev.ntb_hw.0.active=0/1: Like ifconfig 'status' Reviewed by: ngie Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D6429
* sys/dev: minor spelling fixes.pfg2016-05-031-2/+2
| | | | Most affect comments, very few have user-visible effects.
* As <machine/pmap.h> is included from <vm/pmap.h>, there is no need toskra2016-02-222-2/+0
| | | | | | | include it explicitly when <vm/pmap.h> is already included. Reviewed by: alc, kib Differential Revision: https://reviews.freebsd.org/D5373
* NTB: workaround for high traffic hardware hangcem2016-02-143-35/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch comes from Dave Jiang's Linux tree, davejiang/ntb. It hasn't been accepted into Linus' tree, so I do not have an authoritative SHA1 to point at. Original commit log: ===================================================================== A hardware errata causes the NTB to hang when heavy bi-directional traffic in addition to the usage of BAR0/1 (where the registers reside, including the doorbell registers to trigger interrupts). This workaround is only available on Haswell and Broadwell platform. The workaround is to enable split BAR in the BIOS to allow the 64bit BAR4 to be split into two 32bit BAR4 and BAR5. The BAR4 shall be pointed to LAPIC region of the remote host. We will bypass the db mechanism and directly trigger the MSIX interrupts. The offsets and vectors are exchanged during transport scratch pad negotiation. The scratch pads are now overloaded in order to allow the exchange of the information. This gets around using the doorbell and prevents the lockup with additional pcode changes in BIOS. Signed-off-by: Dave Jiang <dave.jiang@intel.com> ===================================================================== Notable changes in the FreeBSD version of this patch: * The MSIX BAR is configurable, like hw.ntb.b2b_mw_idx (msix_mw_idx). The Linux version of the patch only uses BAR4. * MSIX negotiation aborts if the link goes down. Obtained from: Linux (Dual BSD/GPL driver) Sponsored by: EMC / Isilon Storage Division
* ntb_hw(4): Print correct PAT name for non-WC/WB types mapped at loadcem2016-02-101-4/+28
| | | | Sponsored by: EMC / Isilon Storage Division
* ntb_hw(4): Allow any x86 PAT caching flags for MW defaultscem2016-02-101-11/+44
| | | | | | | | | | | | Replace the hw.ntb.enable_writecombine tunable with hw.ntb.default_mw_pat. It can be set with several specific numerical values to select a caching type. Any bogus value is treated as Uncacheable (UC). The ntb_mw_set_wc() KPI has removed the restriction that the selected mode must be one of UC, WC, or WB. Sponsored by: EMC / Isilon Storage Division
* if_ntb: Don't roundup MW size to full BAR size unnecessarilycem2015-12-031-1/+1
| | | | | | | | | | | | | | | Note that the MW allocation still must be BAR *aligned*. So, this only loosens the constraints on MW allocation slightly. BAR-aligned does not play well with large (GB+) BAR sizes. Going forward, if anyone cares about if_ntb on very large BARs, I suggest they add functionality to allocate a smaller window than the BAR size, and set the BAR range to cover a window much larger than the allocated window. This will require negotiating a window offset and limit for protocol traffic. None of this is implemented in this revision. Sponsored by: EMC / Isilon Storage Division
* if_ntb: Log error *before* zeroing relevant variablescem2015-12-031-2/+2
| | | | Sponsored by: EMC / Isilon Storage Division
* NTB: WC/WB isn't enough; set MMR region as UCcem2015-11-252-28/+37
| | | | | | | | And expose vm_memattr_t of current mapping to consumers (as well as the ability to change it to one of UC, WB, WC). After short discussion with: jhb (but no review) Sponsored by: EMC / Isilon Storage Division
* ntb: Add MW tunable for MMR Xeon errata workaroundcem2015-11-241-29/+57
| | | | | | | | | | | | | | | | | | | | Adds a new tunable, ntb.hw.b2b_mw_idx, which specifies the offset (from the total number of memory windows) to use for register access on hardware with the SDOORBELL_LOCKUP errata. The default is -1, i.e., the last memory window. We map BARs before the b2b_mw_idx is selected, so map them all as memory windows initially. The register memory window should not be write-combined, so we explicitly disable WC on the selected MW later. This introduces a layer of abstraction between consumer memory window indices, which exclude any exclusive errata-workaround BARs, and internal memory window indices, which include such BARs. An internal routine, ntb_user_mw_to_idx(), converts the former to the latter. Public APIs have been updated to use this instead of assuming the exclusive workaround BAR is the last available MW. Sponsored by: EMC / Isilon Storage Division
* if_ntb: Initialize if_mtu to the correct MTUcem2015-11-191-1/+6
| | | | | | | Lower the payload data (IP) portion of the MTU from 0x10000 to IP_MAXPACKET (0xFFFF) to avoid panicing the IP stack. Sponsored by: EMC / Isilon Storage Division
* if_ntb: Add Xeon link watchdog register writescem2015-11-193-2/+34
| | | | | | | | | | | This feature is disabled by default. To enable it, tune hw.if_ntb.enable_xeon_watchdog to non-zero. If enabled, writes an unused NTB register every second to demonstrate to a hardware watchdog that the NTB device is still alive. Most machines with NTB will not need this -- you know who you are. Sponsored by: EMC / Isilon Storage Division
* if_ntb: Reuse receive buffers correctlycem2015-11-181-10/+22
| | | | | | | | | | | | | Discard the unused rx_free_q. Instead, reuse inputed packets by putting them back on the *pend* queue after reinitialization. If tx or rx handlers are unavailable, free mbufs rather than leaking them. With this change, if_ntb can receive more than 100 (NTB_QP_DEF_NUM_ENTRIES) packets. Sponsored by: EMC / Isilon Storage Division
* NTB: Expose 32-bit BAR limits to consumerscem2015-11-183-8/+24
| | | | | | | | | | 32-bit BARs can only address memory mapped in the low 32 bits of physical RAM. Expose this as a 'plimit' out parameter from ntb_mw_get_range(). Fix if_ntb to allocate memory within this limit. Sponsored by: EMC / Isilon Storage Division
* NTB: Mask off the low 12 bits of address/range registerscem2015-11-181-6/+7
| | | | | | | | Sometimes they'll read spurious values (observed: 0xc on Broadwell-DE), failing link negotiation. Discussed with: Dave Jiang, Allen Hubbe Sponsored by: EMC / Isilon Storage Division
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