summaryrefslogtreecommitdiffstats
path: root/sys/dev/jme
Commit message (Collapse)AuthorAgeFilesLines
* Add HW MAC counter support for newer JMC250/JMC260 revisions.yongari2008-12-043-24/+197
|
* Add support for newer JMC250/JMC260 revisions.yongari2008-12-043-22/+76
| | | | | | | | | | | | | | | | | | | | | | o Chip full mask revision 2 or later controllers have to set correct Tx MAC and Tx offload clock depending on negotiated link speed. o JMC260 chip full mask revision 2 has a silicon bug that can't handle 64bit DMA addressing. Add workaround to the bug by limiting DMA address space to be within 32bit. o Valid FIFO space of receive control and status register was changed on chip full mask revision 2 or later controllers. For these controllers, use default 16QW as it's supposed to be the safest value for maximum PCIe compatibility. JMicron confirmed performance will not be reduced even if the FIFO space is set to 16QW. o When interface is put into suspend/shutdown state, remove Tx MAC and Tx offload clock to save more power. We don't need Tx clock at all in this state. o Added new register definition for chip full mask revision 2 or later controllers. Thanks to JMicron for their continuous support of FreeBSD.
* Make sure to read the last byte of EEPROM descriptor. Previouslyyongari2008-10-141-5/+5
| | | | | | | | | the last byte of the ethernet address was not read which in turn resulted in getting 5 out of the 6 bytes of ethernet address and always returned ENOENT. I did not notice the bug on FPGA version because of additional configuration data in EEPROM. Pointed out by: bouyer at NetBSD
* Read PCI device id instead of PCI revision id. Also checks the readyongari2008-10-132-2/+4
| | | | | | | device id is JMC260 family. Previously it just verified the deivce is JMC260 Rev A0. This will make it easy for newer JMC2xx support. Pointed out by: bouyer at NetBSD
* Add workaround for occasional packet loss issue of JMC250 A2yongari2008-09-222-3/+20
| | | | | | | | when it runs on half-duplex media. While I'm here add register definition for GPREG1. ATM the GPREG1 register is only valid for JMC250 A1/A2. Submitted by: Ethan at JMicron
* Add workaround for CRC errors seen at 100Mbps on JMC250 A2.yongari2008-09-092-2/+16
| | | | | While here update chip revision number of JMC250/JMC260 from the latest datasheet.
* Fix typo.yongari2008-09-091-1/+1
|
* Fix buffer discard index.yongari2008-07-281-1/+4
| | | | | | | | | While I'm here dicard all buffers if errored frame is part of multi-segmented frames. Pointed out by: sephe Reviewd by: sephe MFC after: 3 days
* Correct 1000Mbps link handling logic for JMC250. This should makeyongari2008-07-181-1/+1
| | | | jme(4) run on 1000Mbps link.
* Add driver support for PCIe adapters based on JMicron JMC250yongari2008-05-273-0/+4325
gigabit ethernet and JMC260 fast ethernet controllers. ATM jme(4) supports all hardware features except RSS and multiple Tx/Rx queue. In these days most ethernet controller vendors take a ply of concealing hardware detailes from open source developers. As contrasted with these vendors JMicron provided all necessary information needed to write a stable driver during driver writing and answered many questions I had. They even helped fixing driver bugs with protocol analyzer. Many thanks to JMicron for their support of FreeBSD. H/W donated by: JMicron
OpenPOWER on IntegriCloud