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* Merge from projects/mips to head by hand:imp2010-01-111-0/+5
| | | | Defintions for cavium uart (do they belong here?)
* add %b formats for various registerssam2009-06-211-0/+12
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* - Cleanup i8251 related defines.nyan2008-09-072-48/+101
| | | | - Move i8255 related defines into a separate file.
* unifdef PC98nyan2008-08-291-2/+0
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* Support for Freescale QUad Integrated Communications Controller.raj2008-03-031-0/+111
| | | | | | | | | | | | | The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500
* Fix style nits. No md5 changes in .o's. ;-)jkim2006-09-081-23/+23
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* Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4.jkim2006-07-061-0/+6
| | | | | | | | | Use it to reset controller and to select data rate. According to Intel 80277AA datasheet, software reset behaves the same as DOR reset except that it is self clearing. National Semiconductor PC8477B datasheet says the same. As a side effect, we no longer use Configuration Control Register (CCR) at 0x3f7 for these controllers, which is often missing in modern hardware.
* Allow uart(4)'s ns8250 driver to work with devices whose regshift is > 0.benno2006-05-231-1/+2
| | | | | | | | | | | | | - Rename REG_DL to REG_DLL and REG_DLH. - Always treat DLL and DLH as two separate 8-bit registers instead of one 16-bit register. Additionally, remove the probe for the high 4 bits of IER being 0 and don't assume we can always read/write 0 to/from those bits. These changes allow uart(4) to drive the UARTs on the Intel XScale PXA255. Reviewed by: marcel
* MFp4:marcel2006-02-241-3/+6
| | | | | Add CHAN_A & CHAN_B for channel register offsets. While here, fix a comment.
* Register definitions for the ancient via6522. This 20+ year-old chipgrehan2005-12-021-0/+105
| | | | | still exists as a cell in the Macio asic on Apples, and is used to communicate through the shift register with the external PMU microcontroller.
* Typo.glebius2005-10-231-1/+1
| | | | | PR: misc/87679 Submitted by: Alan Amesbury <amesbury umn.edu>
* cosmetic change.nyan2005-05-141-1/+1
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* - Move bus dependent defines to {isa,cbus}_dmareg.h.nyan2005-05-141-23/+0
| | | | | | - Use isa/isareg.h rather than <arch>/isa/isa.h. Tested on: i386, pc98
* - Move timerreg.h to <arch>/include and split i8253 specific defines intonyan2005-05-141-0/+78
| | | | | | | | | i8253reg.h, and add some defines to control a speaker. - Move PPI related defines from i386/isa/spkr.c into ppireg.h and use them. - Move IO_{PPI,TIMER} defines into ppireg.h and timerreg.h respectively. - Use isa/isareg.h rather than <arch>/isa/isa.h. Tested on: i386, pc98
* Since we are quite unlikely to ever face another platform whichphk2005-02-061-0/+22
| | | | | | | | | uses the i8237 without trying to emulate the PC architecture move the register definitions for the i8237 chip into the central include file for the chip, except for the PC98 case which is magic. Add new isa_dmatc() function which tells us as cheaply as possible if the terminal count has been reached for a given channel.
* Start each of the license/copyright comments with /*-, minor shuffle of linesimp2005-01-065-5/+5
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* This file was repocopied from sys/dev/uart/uart_dev_z8530.h.marcel2004-11-211-3/+3
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* This file was repocopied from sys/dev/uart/uart_dev_sab82532.h.marcel2004-11-211-0/+5
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* o Remove the com_thr, com_rhr, com_isr and com_lctl defines. They aremarcel2004-11-201-28/+59
| | | | | | | | | | | | | | | | | not used and aliases for other defines. o Add REG_DATA as an alias for com_data. Likewise for other register defines. o Add LCR_SBREAK and make CFCR_SBREAK an alias for it. Likewise for the other LCR register bits that are known with the CFCR prefix. o Add MCR_IE and make MCR_IENABLE an alias for it. o Add LSR_TEMT and make LSR_TSRE an alias for it. o Add LSR_THRE and make LSR_TXRDY as alias for it. o Add FCR_ENABLE and make FIFO_ENABLE as alias for it. Likewise for the other FCR register bits that are known with the FIFO prefix. o Add EFR_CTS and make EFR_AUTOCTS an alias for it. o Add EFR_RTS and make EFR_AUTORTS an alias for it. This is a first step in cleaning up the definitions in this file.
* Remove advertising clause from University of California Regent'simp2004-04-073-12/+0
| | | | | | | license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson. Approved by: core, peter, alc, rwatson
* Add a header for the i8259A register definitions. This is based onjhb2004-01-061-0/+86
| | | | | | | | | | additions to sys/amd64/isa/icu.h from PIIX4 and other datasheets. I tweaked a few comments based on the NetBSD header of the same name when I merged the constants to sys/i386/isa/icu.h, but the vast majority of this file was created independently by Peter and not taken from any existing files. Submitted by: peter
* Added definitions of most of the interesting 16950 register numbersbde2003-09-161-0/+41
| | | | | | | and some of their bits (i.e., fifo trigger levels, frequency multipliers and divisors, and bits to select the registers for these). This attempts to completely describe the 16950's complicated register selects for 16950-specific registers only.
* Added definitions for some 16650 features (mostly misfeatures). Thisbde2003-09-161-0/+7
| | | | completes defining the 16650 register numbers but not all of their bits.
* Fixed a minor error in the description of the EFR and a major error inbde2003-09-161-8/+17
| | | | | | | | | | | | the description of the data latch registers (they were described as readonly). Added some better and worse aliases for standard registers, mostly taken from the 16950 data sheet. Define deprecated aliases in terms of the preferred one. Don't define com_efr in terms of com_fifo. It is unrelated (in a different bank).
* Sorted register numbers together with the correspoding register bits.bde2003-09-161-33/+35
| | | | | | | | Merged comments to match (put them at the right of the #defines instead of duplicating them). Sorted the resulting sections on UART type and register bank. Added a comment for each bank.
* Moved the definitions of the bits in the ns*50 registers from sioreg.hbde2003-09-161-0/+85
| | | | | | | | to ns16550.h. The organization of these files was sort of backwards. The bits in the registers have no driver or bus dependencies but they but the offsets of the registers in bus space are very bus-dependent. However, it does no harm to keep the definitions of the register offsets in ns16550.h provided they are thought of as internal ns*50 offsets.
* The uart(4) driver is an universal driver for various UART hardware.marcel2003-09-062-0/+572
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It improves on sio(4) in the following areas: o Fully newbusified to allow for memory mapped I/O. This is a must for ia64 and sparc64, o Machine dependent code to take full advantage of machine and firm- ware specific ways to define serial consoles and/or debug ports. o Hardware abstraction layer to allow the driver to be used with various UARTs, such as the well-known ns8250 family of UARTs, the Siemens sab82532 or the Zilog Z8530. This is especially important for pc98 and sparc64 where it's common to have different UARTs, o The notion of system devices to unkludge low-level consoles and remote gdb ports and provides the mechanics necessary to support the keyboard on sparc64 (which is UART based). o The notion of a kernel interface so that a UART can be tied to something other than the well-known TTY interface. This is needed on sparc64 to present the user with a device and ioctl handling suitable for a keyboard, but also allows us to cleanly hide an UART when used as a debug port. Following is a list of features and bugs/flaws specific to the ns8250 family of UARTs as compared to their support in sio(4): o The uart(4) driver determines the FIFO size and automaticly takes advantages of larger FIFOs and/or additional features. Note that since I don't have sufficient access to 16[679]5x UARTs, hardware flow control has not been enabled. This is almost trivial to do, provided one can test. The downside of this is that broken UARTs are more likely to not work correctly with uart(4). The need for tunables or knobs may be large enough to warrant their creation. o The uart(4) driver does not share the same bumpy history as sio(4) and will therefore not provide the necessary hooks, tweaks, quirks or work-arounds to deal with once common hardware. To that extend, uart(4) supports a subset of the UARTs that sio(4) supports. The question before us is whether the subset is sufficient for current hardware. o There is no support for multiport UARTs in uart(4). The decision behind this is that uart(4) deals with one EIA RS232-C interface. Packaging of multiple interfaces in a single chip or on a single expansion board is beyond the scope of uart(4) and is now mostly left for puc(4) to deal with. Lack of hardware made it impossible to actually implement such a dependency other than is present for the dual channel SAB82532 and Z8350 SCCs. The current list of missing features is: o No configuration capabilities. A set of tunables and sysctls is being worked out. There are likely not going to be any or much compile-time knobs. Such configuration does not fit well with current hardware. o No support for the PPS API. This is partly dependent on the ability to configure uart(4) and partly dependent on having sufficient information to implement it properly. As usual, the manpage is present but lacks the attention the software has gotten.
* - Clean up function calling conventions.mdodd2003-03-281-0/+2
| | | | | | - Be consistent about what we call our softc. - Minor formatting. - Add some register definitions gleaned from NetBSD/Linux.
* Move the com_scr register address definition over with the other seven.phk2002-09-221-0/+1
| | | | Approved by: bde
* Oops, forgot to commit one file in the fd driver mega update. Here itjoerg2001-12-161-17/+22
| | | | | | is, some more constants for NE765 & Co. Pointed out by: silby, Dave Cornejo <dave@dogwood.com>
* Moved the wd33c93 specific file to sys/dev/ic.nyan2001-06-141-0/+165
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* Move the files from i386/isa/ic/ to dev/ic/.nyan2001-06-102-0/+236
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* Added ESP98 specific register (merged from i386/isa/ic/esp.h).nyan2001-06-101-0/+1
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* Removed unneeded pc98 code (merged from i386/isa/ic/ns16550.h).nyan2001-06-101-14/+0
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* Add $FreeBSD$peter2000-05-011-0/+2
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* $Id$ -> $FreeBSD$peter1999-08-287-7/+7
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* Fixed 10 out of 40 lines of -Wcast-qual warnings/errors. 3 lines werebde1999-05-131-4/+11
| | | | | for old confusion of `volatile char *' with `volatile caddr_t'. 7 lines were for not being careful about aligning pointers to volatiles.
* Implemented sending of BREAKs. This is quite complicated because thebde1998-12-171-1/+6
| | | | | | | | hardware is interrupt-driven to a fault and sending a BREAK requires mode switching. Always running in the BREAK-capable mode as in PR 8318 would double the overhead for sending \0's. Reminded by: PR 8318
* Use [u]intptr_t instead of [unsigned] long to convert and/or representbde1998-08-101-2/+2
| | | | | | | pointers. This finishes fixing conversions between pointers and integers of possibly different sizes in GENERIC.
* Support compiling with `gcc -ansi'.bde1998-04-151-4/+4
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* Enable the FIFO on enhanced floppy controllers. This reduces thetegge1997-09-171-1/+2
| | | | | | | | number of dma overruns/underruns for systems under heavy dma load. As a side effect, broken enhanced floppy controllers that sometimes don't detect dma overruns/underruns will give less errors. Reviewed by: j@uriah.heep.sax.de (J Wunsch)
* Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are notpeter1997-02-227-7/+7
| | | | ready for it yet.
* Make the long-awaited change from $Id$ to $FreeBSD$jkh1997-01-147-7/+7
| | | | | | | | This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long. Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
* A #define really don't need a ; at the end.jhay1996-10-281-2/+2
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* Another round of merge/update.asami1996-09-121-2/+15
| | | | | | | | | (1) Add PC98 support to apm_bios.h and ns16550.h, remove pc98/pc98/ic (2) Move PC98 specific code out of cpufunc.h (to pc98.h) (3) Let the boot subtrees look more alike Submitted by: The FreeBSD(98) Development Team <freebsd98-hackers@jp.freebsd.org>
* Changes to the Digi/Arnet SYNC driver:peter1996-03-171-1/+7
| | | | | | | | | | | | | | | | | | 1. Create 2 x 8k transmit buffer blocks in place of the 16k block previously. With this change the speed as tested with ttcp on a 2Mbit link went up from 206kbyte/s to 236kbyte/s. 2. Change the rest of the functions to also have the definition of the return value on a sepperate line. 3. Remove some unused variables. 4. Add code to recover from DMA underruns. 5. Reorder ar_get_packets() to handle errors better. 6. Only allocate a mbuf cluster if the data is more than the mbuf. (and in a second diff in addition to the above) 7. Stops the occasional DMA underruns that occurred when 2 channels are running at 2Mbit/s. Submitted by: John Hay <jhay@mikom.csir.co.za>
* Oops, this should have been committed with the other Hayes ESP changes.bde1995-12-291-0/+76
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* This driver supports the Arnet SYNC/570i ISA cards that is based on thepeter1995-11-211-0/+366
| | | | | | | | | | | | | | | | | HD64570 chip. Both the 2 and 4 port cards is supported and auto detected. Line speeds of up to 2Mbps is possible. At this speed about 85% of the bandwidth is usable with 486DX processors. The standard FreeBSD sppp code is used for the link level layer. The default protocol used is PPP. The Cisco HDLC protocol can be used by adding "link2" to the ifconfig line in /etc/sysconfig or where ever ifconfig is run. At the moment only the V.35 and X.21 interfaces is supported. The others may need tweaks to the clock selection code. Submitted by: John Hay <jhay@mikom.csir.co.za>
* Staticized an inline function. All inlines in kernel headers should bebde1995-11-181-2/+2
| | | | | static. The function shouldn't be here anyway. It is driver dependent, while `ic' files are supposed to only depend on the IC.
* Cleanup, make things static.phk1995-10-311-3/+3
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