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* MFC r261173jhibbits2014-03-021-0/+1
| | | | MPC74xx should not fall through, to the error case.
* MFC r258779,r258780,r258787,r258822:eadler2014-02-041-1/+1
| | | | | | | | | | | | | Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.
* MFC r259394,r259395,r259699jhibbits2014-01-151-7/+18
| | | | | | | | | r259394: Rebase the PMC indices at 1, since PMC_SOFT is at 0. r259395,r259699: Add userland PMC backtracing, and use the PMC trapframe macros for kernel backtraces.
* Remove local change leftover, this should never have been part ofdavide2013-09-201-2/+0
| | | | | | | r255745. Pointy-hat to: davide Approved by: re (implicit)
* Fix lc_lock/lc_unlock() support for rmlocks held in shared mode. Withdavide2013-09-201-0/+2
| | | | | | | | | | | | | | | current lock classes KPI it was really difficult because there was no way to pass an rmtracker object to the lock/unlock routines. In order to accomplish the task, modify the aforementioned functions so that they can return (or pass as argument) an uinptr_t, which is in the rm case used to hold a pointer to struct rm_priotracker for current thread. As an added bonus, this fixes rm_sleep() in the rm shared case, which right now can communicate priotracker structure between lc_unlock()/lc_lock(). Suggested by: jhb Reviewed by: jhb Approved by: re (delphij)
* Fix the build.jhibbits2013-09-051-0/+2
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* Change the cap_rights_t type from uint64_t to a structure that we can extendpjd2013-09-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in the future in a backward compatible (API and ABI) way. The cap_rights_t represents capability rights. We used to use one bit to represent one right, but we are running out of spare bits. Currently the new structure provides place for 114 rights (so 50 more than the previous cap_rights_t), but it is possible to grow the structure to hold at least 285 rights, although we can make it even larger if 285 rights won't be enough. The structure definition looks like this: struct cap_rights { uint64_t cr_rights[CAP_RIGHTS_VERSION + 2]; }; The initial CAP_RIGHTS_VERSION is 0. The top two bits in the first element of the cr_rights[] array contain total number of elements in the array - 2. This means if those two bits are equal to 0, we have 2 array elements. The top two bits in all remaining array elements should be 0. The next five bits in all array elements contain array index. Only one bit is used and bit position in this five-bits range defines array index. This means there can be at most five array elements in the future. To define new right the CAPRIGHT() macro must be used. The macro takes two arguments - an array index and a bit to set, eg. #define CAP_PDKILL CAPRIGHT(1, 0x0000000000000800ULL) We still support aliases that combine few rights, but the rights have to belong to the same array element, eg: #define CAP_LOOKUP CAPRIGHT(0, 0x0000000000000400ULL) #define CAP_FCHMOD CAPRIGHT(0, 0x0000000000002000ULL) #define CAP_FCHMODAT (CAP_FCHMOD | CAP_LOOKUP) There is new API to manage the new cap_rights_t structure: cap_rights_t *cap_rights_init(cap_rights_t *rights, ...); void cap_rights_set(cap_rights_t *rights, ...); void cap_rights_clear(cap_rights_t *rights, ...); bool cap_rights_is_set(const cap_rights_t *rights, ...); bool cap_rights_is_valid(const cap_rights_t *rights); void cap_rights_merge(cap_rights_t *dst, const cap_rights_t *src); void cap_rights_remove(cap_rights_t *dst, const cap_rights_t *src); bool cap_rights_contains(const cap_rights_t *big, const cap_rights_t *little); Capability rights to the cap_rights_init(), cap_rights_set(), cap_rights_clear() and cap_rights_is_set() functions are provided by separating them with commas, eg: cap_rights_t rights; cap_rights_init(&rights, CAP_READ, CAP_WRITE, CAP_FSTAT); There is no need to terminate the list of rights, as those functions are actually macros that take care of the termination, eg: #define cap_rights_set(rights, ...) \ __cap_rights_set((rights), __VA_ARGS__, 0ULL) void __cap_rights_set(cap_rights_t *rights, ...); Thanks to using one bit as an array index we can assert in those functions that there are no two rights belonging to different array elements provided together. For example this is illegal and will be detected, because CAP_LOOKUP belongs to element 0 and CAP_PDKILL to element 1: cap_rights_init(&rights, CAP_LOOKUP | CAP_PDKILL); Providing several rights that belongs to the same array's element this way is correct, but is not advised. It should only be used for aliases definition. This commit also breaks compatibility with some existing Capsicum system calls, but I see no other way to do that. This should be fine as Capsicum is still experimental and this change is not going to 9.x. Sponsored by: The FreeBSD Foundation
* Fix hwpmc(4) for 32-bit PowerPC.jhibbits2013-09-042-8/+2
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* Refactor PowerPC hwpmc(4) driver into generic and specific. More refactoringjhibbits2013-09-033-714/+852
| | | | | will likely be done as more drivers are added, since AIM-compatible processors have similar PMC configuration logic.
* Complete r250105. Do not zero fields if M_ZERO flag is specified todavide2013-09-011-6/+0
| | | | | | malloc(9). Reported by: pluknet, glebius
* Remove the duplicate LLC_MISS event and put it in the right order.adrian2013-08-291-3/+2
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* Update the mis-predicted branch PMC names (for sandy bridge) to not clash.adrian2013-08-251-2/+2
| | | | | | | | | | | | | | The SDM (June 2013) tables on these are rather confusing. Yes, they assign the same name (BR_MISP_RETIRED.ALL_BRANCHES) to two codes (C5H/00H and C5H/04H.) The latter however is the PEBS version. So, to make it easier to see the difference - and yes, we can use both without having to actually enable the PEBS specific bits! - just rename the PEBS one to _PS so there's no clashing. Tested: * Sandy bridge
* Fix a >80 character long line, introduced in my previous commit.adrian2013-08-251-1/+2
| | | | Noticed by: hiren
* Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandyadrian2013-08-252-24/+35
| | | | | | | | | | | | | | | | | | bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
* Rename the kld_unload event handler to kld_unload_try, and add a newmarkj2013-08-241-58/+53
| | | | | | | | | | | | | | kld_unload event handler which gets invoked after a linker file has been successfully unloaded. The kld_unload and kld_load event handlers are now invoked with the shared linker lock held, while kld_unload_try is invoked with the lock exclusively held. Convert hwpmc(4) to use these event handlers instead of having kern_kldload() and kern_kldunload() invoke hwpmc(4) hooks whenever files are loaded or unloaded. This has no functional effect, but simplifes the linker code somewhat. Reviewed by: jhb
* Change the name of this particular event to reflect the name used inadrian2013-08-211-2/+2
| | | | | | | | | | | | | | | | | | Linux and Intel examples. Sourced: * https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv * http://software.intel.com/en-us/comment/1747932#comment-1747932 Note: * It's not currently in the Intel SDM; I need to chase down what's going on. Tested: * Sandy Bridge
* Correct a typo in the event mask mnemonic.bz2013-08-201-1/+1
| | | | | Reviewed by: gnn MFC after: 3 days
* Add in missing events for Sandy Bridge Xeon.adrian2013-08-182-5/+27
| | | | | | | | | | | | | | | | | * Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy bridge Xeon. Right now it only is enabled for Sandy Bridge. * D2/0F is actually a combination rather than a separate counter, so just flip that on for the CPU types that support it. There's an errata for using this on SB Xeon hardware - I've documented it in kern/181346. Tested: * Sandy Bridge * Sandy Bridge Xeon Sponsored by: Netflix, Inc.
* Relax the vm object locking. Use a read lock.alc2013-06-051-10/+10
| | | | Sponsored by: EMC / Isilon Storage Division
* Suppress a GCC warning. This warning is actually bogus and newer GCCdavide2013-05-021-1/+1
| | | | | | | | versions than the one in base (dim@ mentioned he tried on 4.7.3 and 4.8.1) do not whine about it, so, at some point this workaround will be reverted. Reported by: ache Discussed with: dim
* malloc(9) cannot return NULL if M_WAITOK flag is specified.davide2013-04-302-17/+5
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* The Intel PMC architectural events have encodings which are identical todavide2013-04-302-25/+49
| | | | | | | | | | | | | | | | | those of some non-architectural core events. This is not a problem in the general case as long as there's an 1:1 mapping between the two, but there are few exceptions. For example, 3CH_01H on Nehalem/Westmere represents both unhalted-reference-cycles and CPU_CLK_UNHALTED.REF_P. CPU_CLK_UNHALTED.REF_P on the aforementioned architectures does not measure reference (i.e. bus) but TSC, so there's the need to disambiguate. In order to avoid the namespace collision rename all the architectural events in a way they cannot be ambigous and refactor the architectural events handling function to reflect this change. While here, per Jim Harris request, rename iap_architectural_event_is_unsupported() to iap_event_is_architectural(). Discussed with: jimharris Reviewed by: jimharris, gnn
* Complete r250097:davide2013-04-301-3/+6
| | | | Do not change the initialization order in pmc_intel_initialize().
* When hwpmc(4) module is unloaded it reports a double leakage. This happensdavide2013-04-301-7/+3
| | | | | | | | at least if FreeBSD is ran under VirtualBox. In order to avoid the leakage, properly deallocate structures in case CPU claims that hw performance monitoring counters are not supported. Reported by: hiren
* Fixup Westmere hwpmc(4) support: add missing CPU flag so thatdavide2013-04-301-3/+3
| | | | | | | intrucion-retired, llc-misses and llc-reference events can now be allocated. Reviewed by: jimharris, gnn
* Improve/correct a comment. We now support a lot more cpu types.hiren2013-04-141-1/+1
| | | | | PR: kern/177496 Approved by: sbruno (mentor)
* Cosmetic change: make a comment reference Sandy Bridge *Xeon*rstone2013-04-121-1/+1
| | | | | Reviewed by: sbruno MFC after: 1 week
* Trailing whitespace cleanup along with 80 column enforcemnt.sbruno2013-04-034-1682/+1803
| | | | | | | Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Update hwpmc to support Haswell class processors.sbruno2013-03-284-187/+532
| | | | | | | | | | | | 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
* MFCattilio2013-03-081-6/+15
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| * Add a generic way to call per event allocate / release function.fabient2013-03-051-6/+15
| | | | | | | | | | Reviewed by: mav MFC after: 1 month
| * Add support for good old 8192Hz profiling clock to software PMC.mav2013-02-261-3/+6
| | | | | | | | Reviewed by: fabient
| * Change the way how software PMC updates counters.mav2013-02-261-2/+6
| | | | | | | | | | | | This at least fixes -n option of pmcstat. Reviewed by: fabient
* | MFCattilio2013-02-261-3/+6
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* | MFCattilio2013-02-261-2/+6
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* | Rename VM_OBJECT_LOCK(), VM_OBJECT_UNLOCK() and VM_OBJECT_TRYLOCK() toattilio2013-02-201-10/+10
| | | | | | | | | | | | their "write" versions. Sponsored by: EMC / Isilon storage division
* | Switch vm_object lock to be a rwlock.attilio2013-02-201-0/+1
|/ | | | | | | | * VM_OBJECT_LOCK and VM_OBJECT_UNLOCK are mapped to write operations * VM_OBJECT_SLEEP() is introduced as a general purpose primitve to get a sleep operation using a VM_OBJECT_LOCK() as protection * The approach must bear with vm_pager.h namespace pollution so many files require including directly rwlock.h
* Update hwpmc to support the Xeon class of Ivybridge processors.sbruno2013-01-313-191/+428
| | | | | | | | | | | | | | case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Quiesce a couple of clang warningssbruno2013-01-122-2/+2
| | | | | Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Obtained from: Yahoo! Inc
* Fixup r240246: hwpmc needs to retain the pinning until ASTs are notattilio2012-10-301-1/+1
| | | | | | | | | | | | | executed. This means past the point where userret() is generally executed. Skip the td_pinned check if a callchain tracing is currently happening and add a more robust check to pmc_capture_user_callchain() in order to catch td_pinned leak past ast() in hwpmc case. Reported and tested by: fabient MFC after: 1 week X-MFC: r240246
* Cleanup and rename some variables in libpmc and hwpmc.sbruno2012-10-241-5/+5
| | | | | | | Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ sbruno@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Remove the support for using non-mpsafe filesystem modules.kib2012-10-221-3/+0
| | | | | | | | | | | | In particular, do not lock Giant conditionally when calling into the filesystem module, remove the VFS_LOCK_GIANT() and related macros. Stop handling buffers belonging to non-mpsafe filesystems. The VFS_VERSION is bumped to indicate the interface change which does not result in the interface signatures changes. Conducted and reviewed by: attilio Tested by: pho
* Update hwpmc to support the Xeon class of Sandybridge processors.sbruno2012-10-193-211/+532
| | | | | | | | | | | | | | (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
* hwpmc amd_pcpu_fini: fix a bug in code locked under DEBUGavg2012-09-181-1/+1
| | | | MFC after: 16 days
* Remove all the checks on curthread != NULL with the exception of some MDattilio2012-09-132-9/+3
| | | | | | | | | | | trap checks (eg. printtrap()). Generally this check is not needed anymore, as there is not a legitimate case where curthread != NULL, after pcpu 0 area has been properly initialized. Reviewed by: bde, jhb MFC after: 1 week
* Complete and merge the list between Sandy/Ivy bridge of eventsfabient2012-09-071-28/+18
| | | | | | that can run on specific PMC. MFC after: 1 month
* Add Intel Ivy Bridge support to hwpmc(9).fabient2012-09-064-176/+433
| | | | | | | | | | Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
* Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D).davide2012-06-171-1/+0
| | | | | | | | | Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine. Approved by: gnn (mentor) MFC after: 3 days
* Add ARM callchain support for hwpmc.fabient2012-06-131-12/+92
| | | | | Sponsored by: NETASQ MFC after: 3 days
* Soft PMC support for ARM.fabient2012-05-231-8/+17
| | | | | | Callgraph is not captured, only current location. Sample system wide profiling: "pmcstat -Sclock.hard -T"
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