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* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-4/+5
| | | | Reviewed by: jhb, peter (early amd64 version)
* - Separate PMC class dependent code from other kinds of machinejkoshy2008-11-091-116/+15
| | | | | | | | | | | | | | | | | dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
* Retire the MALLOC and FREE macros. They are an abomination unto style(9).des2008-10-231-2/+2
| | | | MFC after: 3 months
* Correct a callchain capture bug on the i386.jkoshy2008-09-151-3/+3
| | | | | | | | | | | | | On the i386 architecture, the processor only saves the current value of `%esp' on stack if a privilege switch is necessary when entering the interrupt handler. Thus, `frame->tf_esp' is only valid for an entry from user mode. For interrupts taken in kernel mode, we need to determine the top-of-stack for the interrupted kernel procedure by adding the appropriate offset to the current frame pointer. Reported by: kris, Fabien Thomas Tested by: Fabien Thomas <fabien.thomas at netasq dot com>
* Kernel and hwpmc(4) support for callchain capture.jkoshy2007-12-071-0/+191
| | | | Sponsored by: FreeBSD Foundation and Google Inc.
* Revert revision 1.4.jkoshy2007-11-291-1/+1
| | | | | | | | | | Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM)) have a PMC architecture that differs somewhat from previous CPUs in family 0x6. Even though the basic programming model is similar, the documented set of legal values that may be loaded into their PMC MSRs differs from that of the previous PMCs in family 0x6 and reusing bit values valid for the older PMCs could result in undefined behaviour in the general case.
* Add support for Intel cpu model's 5 & 6.ps2006-04-041-1/+1
| | | | Approved by: jkoshy
* Add support for a new/unreleased Pentium-M.ps2005-11-181-1/+1
| | | | Reviewed by: jkoshy
* On x86 processors, turn off any 'INTERRUPT' capabilities on PMCsjkoshy2005-08-221-3/+13
| | | | | | if the CPU does not have its local APIC enabled. MFC after: 3 days
* - Update the CPU version check to recognize P4/EMT64 CPUs. [1]jkoshy2005-07-031-1/+1
| | | | | | | | | - Allow libpmc(3) to support P4/EMT64 PMCs on the amd64 architecture and AMD K8 PMCs on the i386. [2] Submitted by: ps [1] Pointy hat: myself [2] Approved by: re (scottl)
* MFP4:jkoshy2005-06-091-0/+179
- Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
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