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* MFH: r259647julian2016-10-071-4/+12
| | | | | | | | | | | | o Remove assertions on ipa_version as sometimes the version detection using cpuid can be quirky (this is the case of VMWare without the vPMC support) but fail to probe hwpmc. o Apply the fix for XEON family of processors as established by 315338-020 document (bug AJ85). Sponsored by: EMC / Isilon storage division Reviewed by: fabient MFC courtesy of panzura.
* MFC 282641,282658:jhb2015-06-011-4/+4
| | | | | | | | - Move hwpmc(4) debugging code under a new HWPMC_DEBUG option instead of the broader DEBUG option. - Convert hwpmc(4) debug printfs over to KTR. Sponsored by: Norse Corp, Inc.
* MFC of r277177 and r279894 with the fixes for the PMC for Haswell.rrs2015-03-241-0/+9
| | | | Sponsored by: Netflix Inc.
* MFC r267062:kib2014-06-181-1/+12
| | | | Disable existing uncore hwpmc code for Nehalem and Westmere EX.
* MFC r263446hiren2014-05-311-0/+6
| | | | | Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014)
* Complete r250097:davide2013-04-301-3/+6
| | | | Do not change the initialization order in pmc_intel_initialize().
* When hwpmc(4) module is unloaded it reports a double leakage. This happensdavide2013-04-301-7/+3
| | | | | | | | at least if FreeBSD is ran under VirtualBox. In order to avoid the leakage, properly deallocate structures in case CPU claims that hw performance monitoring counters are not supported. Reported by: hiren
* Trailing whitespace cleanup along with 80 column enforcemnt.sbruno2013-04-031-4/+10
| | | | | | | Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Update hwpmc to support Haswell class processors.sbruno2013-03-281-0/+8
| | | | | | | | | | | | 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Update hwpmc to support the Xeon class of Ivybridge processors.sbruno2013-01-311-0/+6
| | | | | | | | | | | | | | case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Update hwpmc to support the Xeon class of Sandybridge processors.sbruno2012-10-191-0/+6
| | | | | | | | | | | | | | (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
* Add Intel Ivy Bridge support to hwpmc(9).fabient2012-09-061-0/+6
| | | | | | | | | | Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
* Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D).davide2012-06-171-1/+0
| | | | | | | | | Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine. Approved by: gnn (mentor) MFC after: 3 days
* Remove out of date KASSERT that fire with soft PMC.fabient2012-05-101-12/+0
| | | | MFC after: 1 week
* Add software PMC support.fabient2012-03-281-4/+2
| | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
* Fix crash on VirtualBox (and probably on some real hardware):gonzo2012-03-271-0/+3
| | | | | | | | - Do not cover error returned by pmc_core_initialize with the result of pmc_uncore_initialize, fail right away. - Give a user something to report instead failing silently Reported by: Alexandr Kovalenko <never@nevermind.kiev.ua>
* - Add support for the Intel Sandy Bridge microarchitecture (both core and ↵davide2012-03-011-0/+9
| | | | | | | | | | | uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
* - Support for uncore counting events: one fixed PMC with the uncorefabient2010-04-021-1/+40
| | | | | | | | | | | | domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
* Recognize Intel CPUs with Family 0x6, Models 0x1E and 0x1F.jkoshy2009-12-181-0/+2
| | | | Submitted by: Marc Unangst <mju at panasas dot com>
* - Add support for nehalem/corei7 cpus. This supports all of the corejeff2009-01-271-0/+5
| | | | | | | | counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
* Fixes for Core2 Extreme support.jkoshy2008-12-031-0/+2
| | | | Submitted by: "Artem Belevich" <artemb at gmail dot com>
* - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solojkoshy2008-11-271-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-1/+2
| | | | Reviewed by: jhb, peter (early amd64 version)
* Fix assertions.jkoshy2008-11-151-6/+9
| | | | Reported by: keramida
* - Separate PMC class dependent code from other kinds of machinejkoshy2008-11-091-0/+227
| | | | | | | | | | | | | | | | | dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
* MFP4:jkoshy2005-06-091-143/+0
| | | | | | | | | | | | | | | | - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
* Add convenience APIs pmc_width() and pmc_capabilities() to -lpmc.jkoshy2005-05-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Have pmcstat(8) and pmccontrol(8) use these APIs. Return PMC class-related constants (PMC widths and capabilities) with the OP GETCPUINFO call leaving OP PMCINFO to return only the dynamic information associated with a PMC (i.e., whether enabled, owner pid, reload count etc.). Allow pmc_read() (i.e., OPS PMCRW) on active self-attached PMCs to get upto-date values from hardware since we can guarantee that the hardware is running the correct PMC at the time of the call. Bug fixes: - (x86 class processors) Fix a bug that prevented an RDPMC instruction from being recognized as permitted till after the attached process had context switched out and back in again after a pmc_start() call. Tighten the rules for using RDPMC class instructions: a GETMSR OP is now allowed only after an OP ATTACH has been done by the PMC's owner to itself. OP GETMSR is not allowed for PMCs that track descendants, for PMCs attached to processes other than their owner processes. - (P4/HTT processors only) Fix a bug that caused the MI and MD layers to get out of sync. Add a new MD operation 'get_config()' as part of this fix. - Allow multiple system-mode PMCs at the same row-index but on different CPUs to be allocated. - Reject allocation of an administratively disabled PMC. Misc. code cleanups and refactoring. Improve a few comments.
* Include <sys/pmc.h> instead of <machine/pmc_mdep.h>. The MI headermarcel2005-04-201-2/+1
| | | | | | | | includes the MD header for us. Do not include <machine/specialreg.h> as it is not a header file that can be included from MI files. It is included from <machine/pmc_mdep.h> if so needed and possible. Ok'd: jkoshy@
* Bring a working snapshot of hwpmc(4), its associated libraries, userland ↵jkoshy2005-04-191-0/+142
utilities and documentation into -CURRENT. Bump FreeBSD_version. Reviewed by: alc, jhb (kernel changes)
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