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* Fix the port based vlans for the Marvell e6000 series switches.Luiz Souza2017-07-172-92/+87
| | | | (cherry picked from commit b9f3af6b8a65f84f59910eac8f0f25655843059d)
* Add support to 2.5G uplink for the MV88E6141 and MV88E6341 switches.loos2017-07-172-43/+111
| | | | | | | | | Force the switch port settings for fixed media types. Tested with: 88E6176, 88E6141 Sponsored by: Rubicon Communications, LLC (Netgate) (cherry picked from commit 3ba75ba1dd1d3a57786548860363a11f012f78c6)
* Prevent multiple lock initialization in e6000sw probezbb2017-07-171-3/+8
| | | | | | | | | | | | | | | r319886 ("Add the initial support for the Marvell 88E6141 and 88E6341 switches.") unveiled a problem with possible multiple lock creation. Move its initialization to the driver attach and for obtaining the switch ID create a temprorary one, which is immediately destroyed after the check. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf (cherry picked from commit de899400f853ef674c219fd03a48215aadbcf647)
* Add the initial support for the Marvell 88E6141 and 88E6341 switches.loos2017-07-171-18/+66
| | | | | | | | | | | | Right now the driver only supports port VLANs, so make sure etherswitch_getinfo() return the proper switch capabilities. Handle the cases where not all ports are in use (that will also require etherswitch cooperation). Sponsored by: Rubicon Communications, LLC (Netgate) (cherry picked from commit c91f28aeedeb85cccd12ab1a8af23675a563b6fe)
* [etherswitch] add in an initial API for controlling per-port LED behaviour.adrian2017-07-175-4/+146
| | | | | | | | This is just implemented for the AR8327 for now. Submitted by: Dan Nelson <dnelson_1901@yahoo.com> (cherry picked from commit d57c6dcdab1f6ac68de08e6d3bcc58ba374afbb2)
* Remove an unnecessary variable from the switch softc structure and make theloos2017-07-171-19/+22
| | | | | | functions that are used as booleans return real boolean values. Sponsored by: Rubicon Communications, LLC (Netgate)
* style(9) fixes, remove unnecessary headers, remove duplicate #defines andloos2017-07-172-136/+88
| | | | | | | | | | in some cases, shuffle the code around to simplify locking. No functional changes. Sponsored by: Rubicon Communications, LLC (Netgate) (cherry picked from commit 228e64ca6d855785d04d95b1dbab516e0cdcc2ef)
* Poll PHY status using internal e6000sw registerswma2017-07-172-6/+53
| | | | | | | | | | | | | | | | | | | | | | | e6000sw family automatically reflects PHY status in each port's registers. Therefore it is not necessary to do a full PHY polling squence, which results in much quicker operation and much less significant usage of the SMI bus. Care must be taken that the resulting ifmedia_active is identical to what the PHY will compute, or gratuitous link status changes will occur whenever the PHYs update function is called. This patch implements above improvement. On the occasion set a pointer to the proc structure to be part of software context instead of being a global variable. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10714 (cherry picked from commit 63843c9be40aba2fb7e803960fb7d4fcee1d3eeb)
* Improve busy-wait loop during switch phy access in e6000swwma2017-07-171-8/+39
| | | | | | | | | | | | | | | Hitherto implementation of PHY polling resulted in a risk of an endless loop and very high occupation of the SMI bus. Improve the operation by limiting the polling tries and adding sleepable pause. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10713 (cherry picked from commit b854df5591d7a547679e3e8ee25f39492442b21f)
* Add missing unlock in e6000sw driverzbb2017-07-171-0/+1
| | | | | | | | | | | | This patch adds missing unlock on attach failure. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10712 (cherry picked from commit 13060c90f906f6feb26bdfb2f1b8304de0f6886a)
* Fix broken malloc in e6000swzbb2017-07-171-2/+4
| | | | | | | | | | | | | | | Malloc should always return something when M_WAITOK flag is used, but keep this code and change flag to M_NOWAIT as it is under a lock (allows for possible future change). Free ifnet structure to avoid memory leak on failure. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10711 (cherry picked from commit 9701ccf52d7dd27cf6b73be152060fa3983afbee)
* When the switch is set to operate in the Multi Chip Addressing Mode weloos2017-07-171-13/+7
| | | | | | | | | | | | | | | | | cannot access the GLOBAL2 register directly. Despite the comment in code (which was misleading), the indirect access is only used to read the switch CONFIG data from the scrap register and not for the GLOBAL2 access. Use the dsa data to define when the switch is in the Multi Chip Addressing Mode (a even address different than zero). While here fix a typo. Sponsored by: Rubicon Communications, LLC (Netgate) (cherry picked from commit b0b3a756887e79e36f010e8aaa8f3032d73e1f7c)
* Improve ports handling in e6000sw driverzbb2017-07-172-80/+286
| | | | | | | | | | | | | | | | | | - recognize ports and vlangroups based on DTS file - support multi-chip addresing mode (required in upcoming Armada-388-Clearfog support) - refactor attachment function Each port in 'dsa' node should have 'vlangroup' property. Otherwise, e6000sw will fail to attach. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D7328 (cherry picked from commit 33ec32197181bff1a652a23fd0a470589ca1a520)
* Add a bitmask field to keep the enabled ports of a switch, not all switches ↵Luiz Souza2017-07-171-0/+9
| | | | | | | | will use all the ports, so looping on all ports starting from port 0 was wrong, this commit fixes it. This is an optional feature, so there is now a switch capabilities to keep the state and availability of optional switch features. (cherry picked from commit 78e3f93a8eda5a9968924225ea46756767296ba4)
* MFC r308700:mizhka2017-03-152-222/+335
| | | | | | | | | | | | [etherswitch] add RTL8366SR support Add RTL8366SR support at etherswitch driver. Tested on RTL8366RB and RTL8366SR. Submitted by: Hiroki Mori <yamori813@yahoo.co.jp> Reviewed by: adrian, mizhka Approved by: adrian(mentor) Differential Revision: https://reviews.freebsd.org/D6796
* MFC r311700:loos2017-01-131-6/+13
| | | | | | | | Convert etherswitch to use the make_dev_s(9) KPI. This fix a possible race where si_drv1 can be accessed before it gets set. Suggested by: kib Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r309461:loos2016-12-311-70/+1
| | | | | | | | | | | | Allow simultaneous access to switch device, there is no reason to prevent it. Remove bogus wrappers and use the kernel defaults. While here, use DEVMETHOD_END. Obtained from: pfSense Sponsored by: Rubicon Communications, LLC (Netgate)
* MFC r303891, r303892:pfg2016-09-081-1/+1
| | | | | | | | sys: replace comma with semicolon when pertinent. Uses of commas instead of a semicolons can easily go undetected. The comma can serve as a statement separator but this shouldn't be abused when statements are meant to be standalone.
* Remove erroneous lock assertionssgalabov2016-06-061-2/+0
| | | | | | | | In mediatek etherswitch support, functions mtkswitch_reg_write32_mt7621 and mtkswitch_reg_read32_mt7621 are called without locks held, so lock assertions fail. Remove the lock assertions. Sponsored by: Smartcom - Bulgaria AD
* Fix issues with mt762x etherswitch driversgalabov2016-05-172-9/+20
| | | | | | | | Fix issues that crept in with initial import. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6393
* Introduce basic etherswitch support for Ralink SoCssgalabov2016-05-166-0/+2103
| | | | | | | | | | | | | This revision introduces basic support for the internal ESW switch found Ralink/Mediatek SoCs such as RT3050, RT3352, RT5350, MT7628; and GSW found in MT7620 and MT7621. It only supports 802.1q VLANs and doesn't support external PHYs at the moment (only the ones that are built into the switch itself). Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6348
* sys/dev: minor spelling fixes.pfg2016-05-031-1/+1
| | | | Most affect comments, very few have user-visible effects.
* Cleanup unnecessary semicolons from the kernel.pfg2016-04-104-4/+4
| | | | Found with devel/coccinelle.
* [mdio] migrate mdiobus out of etherswitch and into a top-level device of its ↵adrian2015-12-2615-188/+12
| | | | | | | | | | | own. The mdio driver interface is generally useful for devices that require MDIO without the full MII bus interface. This lifts the driver/interface out of etherswitch(4), and adds a mdio(4) man page. Submitted by: Landon Fuller <landon@landonf.org> Differential Revision: https://reviews.freebsd.org/D4606
* [arswitch] bump the number of ports on the ar934x internal switch.adrian2015-12-151-2/+2
| | | | It indeed has more ports by default.
* Introduce e6000sw etherswitch supportzbb2015-10-252-0/+1161
| | | | | | | | | | | | | | | | | | Add e6000sw driver supporting Marvell 88E6352, 88E6172, 88E6176 switches. It needs to be attached to mdio interface, exporting SMI access functionality. e6000sw supports port-based VLAN configuration, per-port media changing, accessing PHY and switch registers. e6000sw attaches miibuses and PHY drivers as children. Instead of typical tick as callout, kthread-based tick is used. This combined with SX locks allows MDIO read/write calls to sleep. It is expected, because this hardware requires long delays in SMI read/write procedures, which can not be handled by busy-waiting. Reviewed by: adrian Obtained from: Semihalf Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Differential revision: https://reviews.freebsd.org/D3902
* AR8327: Fix up the ability to configure the vlangroup configuration for the ↵adrian2015-10-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | CPU port I messed up when doing the reset_vlans method - setting vid[0] = 1 here was making it 'hidden' from configuration (as it needed ETHERSWITCH_VID_VALID as well) and so there was no way to configure vlangroup0. In per-port VLAN mode, vlangroup0 is for the CPU port (port0). Now, it normally wouldn't really matter - the CPU port thus sees all other ports. However there are two CPU ports on the AR8327 and so port0 (arge0) was seeing all traffic on port6 (arge1). If you thus tried to use arge1/port6 for anything (eg a WAN port) in a bridge group then things would very upset very quickly. Whilst here, add a comment to remind myself that yes, it'd be nice if we could specify a boot-time switch config. Tested: * AP135 reference platform w/ AR8327N switch
* Fix French typos in etherswitch.rpaulo2015-04-181-61/+61
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* Turns out the AR933x looks like the AR7240/AR7241 switch as far as VLANadrian2015-03-281-1/+0
| | | | | | | | | | configuration is concerned. So, remove the now-erroneous comment. Tested: * AR9331 - Carambola2, with transmitting dot1q tagged packets around.
* Commit 802.1q configuration support for the AR8327.adrian2015-03-134-35/+217
| | | | | | | | | | | | | | | | | | | | | | This is slightly different to the other switches - the VLAN table (VTU) programs in the vlan port mapping /and/ the port config (tagged, untagged, passthrough, any.) So: * Add VTU operations to program the VTU (vlan table) * abstract out the mirror-disable function so it's .. well, a function. * setup the port to have a dot1q configuration for dot1q - the port security is VLAN (not per-port VLAN) and requires an entry in the VLAN table; * add set_dot1q / get_dot1q to program the VLAN table; * since the tagged/untagged ports are now programmed into the VTU, rather than global - plumb the ports /and/ untagged ports bitmaps through the arswitch API. Tested: * AP135 - QCA9558 SoC + AR8327N switch
* Methodise a couple more of the VLAN methods.adrian2015-03-084-12/+18
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* Add per-port vlan support for the AR8327.adrian2015-03-086-31/+145
| | | | | | | | | | | | | | | | | | All the per-port support is really doing is applying a port visibility mask to each of the switchports. Everything still look like a single portgroup (vlan id 1), but the per-port visibility mask is modified. Whilst I'm here, also add some initial dot1q support - the pvid stuff is doing the right thing, but it's not useful without the rest of the VLAN table programming. It's enough for me to be able to use the LAN/WAN port distinction on the AP135, where there isn't (for now!) a dedicated PHY for the "WAN" port. Tested: * AP135, QCA9558 SoC + AR8327 switch
* Fix up support for the AR8327.adrian2015-03-086-66/+237
| | | | | | | | | | | | | | | | | | | | * Even though I got the registers around "right", it seems I'm not tickling the MDIO access correctly for the internal PHY bus. Some of the switches are fine poking at the external PHY registers; others aren't. So, enable direct PHY bus access for the AR8327, and leave the existing code in place for the others. * Go and shuffle the register access around. Whilst here, restore the 2ms delay if changing page. * Comment out some of the stub printf()s; there's some upcoming work to add port VLAN support. Tested: * AP135 development board * Carambola2 - AR9331 SoC
* AR8327: Disable energy-efficient ethernet support in the PHYs.adrian2015-03-011-18/+31
| | | | | | | | | I noticed that openwrt/linux does this, citing "instability", so until they figure out why I'm going to disable it here as well. Tested: * QCA AP135 - QCA955x SoC + AR8327 switch.
* Bump the port mask on the AR8327 ethernet switch from 0x3f to 0x7f.adrian2015-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So, it turns out that the AR8327 has 7 ports internally: * GMAC0 / external (CPU) MAC0 * GMAC1 / port1 -> GMAC5 / port5: external switch port PHYs * GMAC6 / external (CPU) MAC1 Now, depending upon how things are wired up, the second CPU port (MAC1) can be wired to either the switch (port6), or through port5's PHY, bypassing the GMAC+switch entirely. Ie, it can pretend to be a boring PHY, saving system designers from having to include a separate PHY for a "WAN" port. Here's the rub - the AP135 board (QCA955x SoC) hooks up arge0 to the second CPU port on the AR8327, but it's hooked up as RGMII. So, in order to hook it up to the rest of the switch, it isn't configured as a separate PHY - OpenWRT has it setup as connected via RGMII to GMAC6 and (I'm guessing) it's set to be a WAN port by configuring up port-based VLANs or something. Thus, with a port mask of 0x3f, GMAC6 was never allowed to receive traffic from any other port. It could transmit fine, but not receive anything. So, now it works enough for me to continue doing board bootstrapping. Note, this isn't enough to make the QCA955x + AR8327 work - there's a bunch of uncommitted work to both the platform SoC (interrupt handling, ethernet, etc) and the ethernet switch (register access space, setup, etc) that needs to happen. However, this particular change is also relevant to other SoCs, like the AR934x and AR7161, both of which can be glued to this switch. Tested: * AP135 development board TODO: * Figure out whether I can somehow abuse another port mode to have this be a pass-through PHY, or whether I should just create some more boot time hints to explicitly set up port-based isolation so this works in a more useful way by default.
* Add another register definition for the AR8327.adrian2015-02-281-0/+3
| | | | Obtained from: OpenWRT
* Add another revision of the AR8327.adrian2014-07-261-0/+1
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* Revert r268543.rpaulo2014-07-1210-10/+10
| | | | We should probably fix sys/gpio.h instead.
* Move iic.h to sys/ so that it's automatically installed in /usr/include/sys.rpaulo2014-07-1210-10/+10
| | | | | | | This lets us call iic(4) ioctls without needing the kernel source code and follows the same model of GPIO. MFC after: 3 weeks
* Allow the PVID setting on CPU port.loos2014-07-051-2/+8
| | | | | | Return our static list of supported media for the CPU port. Tested on TP-Link 1043ND.
* Initialize the switch vlan table at attachment.loos2014-07-031-7/+33
| | | | | | | | | | | | | | | Update some comments on code, specifying the correct vlans used on switch setup. Advertise the proper switch operation mode (the rtl8366rb only support dot1q vlans). This fixes the breakage that i introduced on r249752 and make the rtl8366rb switch works again with etherswitchcfg(8). Tested on TP-Link 1043ND. Tested by: me, Harm Weites (harm at weites.com)
* Fix the reported status for the switch CPU port which was (wrongly)loos2014-07-012-2/+2
| | | | | | reporting half-duplex link. Tested on TP-Link WR1043ND.
* Add the CPU port flag to the CPU port on rtl8366 (port 5).loos2014-07-012-4/+8
| | | | | | Do not allow any media change on the switch CPU port. Tested on TP-Link WR1043ND.
* Fix the build with debug enabled and remove a variable used only at switchloos2014-05-092-11/+4
| | | | initialization, it is nonsense keep it around without futher use.
* Fix a bug on ip17x switch initialization which will fail as soon as youloos2014-05-092-2/+2
| | | | | | | disable the debug and diagnosis options from current. We must wait 2ms after the switch reset and not 2us. Tested on RB433UAH.
* Add a description here.adrian2014-03-021-0/+3
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* Set all of the ports into the same vlangroup; there's only one vlangroupadrian2014-03-021-5/+4
| | | | | | | | | | | | (pvid=1) and we already configure them to send to other ports. Setting pvid=portnum would mean that there were separate vlangroups for each ports, but 'leaking' into other ports. The result? All port traffic flooded to all other port traffic. Tested: * DB120, AR9344 + AR8327 switch
* Add ATU flush support.adrian2014-03-023-1/+79
| | | | | | | | | | | | | | | | | | | The OpenWRT AR8xxx switch support flushes the ATU (address translation unit) after each port link 'up' status change. I've modified this to just flush on any port transition. Whilst here, bump the number of ports on the AR8327 to 6, rather than the default of 5. It's DB120 specific; I'll go and make this configurable later. There's some debugging code in here still; I am still debugging whether this is or isn't working fully. Tested: * DB120, AR9344 + AR8327 switch Obtained from: OpenWRT
* Add AR8216 era ATU management/configuration register definitions.adrian2014-03-021-6/+31
| | | | Obtained from: OpenWRT
* (I think!) make the AR8327 switch correctly handle traffic.adrian2014-03-011-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | This patch does four things: * it globally disables mirroring; * it globally sets the mirroring on each port to be disabled; * the initial port setup now programs a portmask for the port to allow transmission (forwarding) to all other ports bar itself; * the vlan setup path now programs the portmask for the port to allow transmission (forwarding) to all other ports bar itself. Before this, I hard-coded the portmask to 0x3f which would mean all ports (bar port 6, which currently isn't hooked up to anything.) This means that traffic would be duplicated back out the port it received it. I bet this wasn't .. optimal. In any case, this _seems_ to make DHCP from my macosx laptop work through this access point. I'll do some further testing to ensure it's actually working correctly on all my devices. Tested: * DB120, AR8327 switch
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