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* Add the support for 802.1q and port based vlans for arswitch.loos2013-07-2311-70/+660
| | | | | | | | Tested on: RB450G (standalone ar8316), RSPRO (standalone ar8316) and TPLink MR-3220 (ar724x integrated switch). Approved by: adrian (mentor) Obtained from: zrouter
* Fix the arswitch instability problem. It turns out that theloos2013-07-234-27/+9
| | | | | | | | | | | | | | arswitch_writereg() routine was writing the registers in the wrong order. Revert -r241918 as the root problem is now fixed. Remove another workaround from arswitch_ar7240.c. Simplify and fix the code on arswitch_writephy() by using arswitch_writereg(). While here remove a redundant declaration from arswitchvar.h. Approved by: adrian (mentor)
* Add a new flag (ETHERSWITCH_VID_VALID) to say what vlangroups are in use.loos2013-07-235-11/+33
| | | | | | | | | | | | | | This fix the case when etherswitch is printing the information of port 0 vlan group (in port based vlan mode) with no member ports. Add the ETHERSWITCH_VID_VALID support to ip17x driver. Add the ETHERSWITCH_VID_VALID support to rt8366 driver. arswitch doesn't need to be updated as it doesn't support vlans management yet. Approved by: adrian (mentor)
* Bring in a basic ethernet switch driver for the IP17x series ofadrian2013-05-0811-0/+1650
| | | | | | | | | switches. These are notably found on some AR71xx based Mikrotik boards. Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
* Fix the ukswitch code to work with the new vlan changes:adrian2013-05-081-9/+9
| | | | | | | | | | | * Fix API changes; * remove unused code; * Allow some switches to be used that don't expose a set of PHY registers for the CPU facing port (eg the ADM6996 for the Ubiquiti Routerstation.) Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
* Correctly mark the CPU port.adrian2013-05-081-0/+1
| | | | | Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
* Add the ability to change the vlan operation mode.adrian2013-05-083-1/+71
| | | | | | | | | | | | This adds a vlan capability field to etherswitch_info structure and some definitions of ports flags. It adds the support to global config parameters which right now is used only to switch between the vlan modes, but it is intended to be extended to support the setup of others parameters (STP, mirror, etc.). Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
* Update arswitch to the new API.adrian2013-04-221-1/+1
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* Convert over the etherswitch framework to use VLAN IDs per port, ratheradrian2013-04-222-9/+23
| | | | | | | | | | | | | | | | | | | | | than VLAN groups. Some chips (eg this rtl8366rb) has a VLAN group per port - you first define a set of VLANs in a vlan group, then you assign a VLAN group to a port. Other chips (eg the AR8xxx switch chips) have a VLAN ID array per port - there's no group per se, just a list of vlans that can be configured. So for now, the switch API will use the latter and rely on drivers doing the heavy lifting if one wishes to use the VLAN group method. Maybe later on both can be supported. PR: kern/177878 PR: kern/177873 Submitted by: Luiz Otavio O Souza <loos.br@gmail.com> Reviewed by: ray
* Implement a very basic multi-PHY aware switch device.adrian2013-04-191-0/+570
| | | | | | | | | This is intended to be used as a stop-gap for switch devices which expose multiple ethernet PHYs but we don't have a driver for - here, etherswitchcfg and the general switch configuration API can be used to interface to said PHYs. Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
* Disable automatic attachment of arswitch. It can't be auto-detected (like PHYsray2012-11-071-11/+0
| | | | | | | do) and cause a problems trying to attach another instance to child mdio. Submitted by: Luiz Otavio O Souza Approved by: adrian (menthor)
* Don't try to cache the page setting - always set the page beforeadrian2012-10-221-4/+11
| | | | | | doing a switch register read/write. PR: kern/172968
* Mask data to only 16 bits to be sure on write into switch reg.ray2012-10-151-1/+1
| | | | | Submitted by: Luiz Otavio O Souza Approved by: adrian (mentor)
* Locking for etherswitch framework:ray2012-10-154-7/+82
| | | | | | | | | | * add lock/unlock methods; * add lock/unlock default implementation; * surround switch IOCTLs with locking; * add lock/unlock implementation for arswitch; Submitted by: Luiz Otavio O Souza Approved by: adrian (mentor)
* Defaulting to id "0" if ar7240_probe(dev) success, fix warning when buildingray2012-10-151-0/+1
| | | | | | | with DEBUG. Submitted by: Luiz Otavio O Souza Approved by: adrian (mentor)
* Fix tiypo.ray2012-10-111-1/+1
| | | | | Submitted by: Luiz Otavio O Souza Approved by: adrian (mentor)
* Setup the CPU port and broadcast map on the AR7240, rather thanadrian2012-05-122-10/+18
| | | | | | | | | | | | | | | depending upon the bootloader initialising it. The aim is to eventually support a full switch set and reinitialisation rather than relying on a consistent bootloader setup. Remove the port flood config from arswitch.c, it's not yet used and it's totally incorrect. Whilst I'm here, also add in a comment describing why the full switch reset is disabled. Obtained from: Linux (OpenWRT) - Values
* .. oops, include setting the MTU.adrian2012-05-121-1/+4
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* Document what the flood register setting does.adrian2012-05-121-1/+8
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* * Add in the AR7240 global control field for setting the maximum frameadrian2012-05-121-0/+14
| | | | | | | | | | | | | | size for the AR7240. * Include SM/MS macros, thanks to ath_hal(4). * This field is for normal packets, VLAN and other headers are added to this by the switch device. * Set the MTU to 1536, to match what is done in Linux. Use the SM macro to write this field. Obtained from: Atheros (AR7240 datasheet), Linux OpenWRT (MTU default)
* * Remove the AR7240 register defines and reuse the AR8x16 defines.adrian2012-05-122-8/+5
| | | | | | | * Include a new register define to represent "disable port mirroring to CPU port". Obtained from: Patrick Kelsey <kelsey@ieee.org>
* Further arswitch work:adrian2012-05-124-1/+194
| | | | | | | | | | | | | | | | | | | | | | * Add in the AR724x support. It probes the same as an AR8216/AR8316, so just add in a hint to force the probe success rather than auto-detecting it. * Add in the missing entries from conf/files, lacking in the previous commit. The register values and CPU port / mirror port initialisation value was obtained from Linux OpenWRT ag71xx_ar7240.c. The DELAY(1000) to let things settle is my local workaround. For some reason, PHY4 doesn't seem to probe very reliably without it. It's quite possible that we're missing some MDIO bus initialisation code in if_arge for the AR724x case. As I dislike DELAY() workarounds in general, it's definitely worth trying to figure out why this is the case. Tested on: AP93 (AR7240) reference design Obtained from: Linux OpenWRT
* Commit the first pass of the etherswitch support.adrian2012-05-1118-0/+3090
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is designed to support the very basic ethernet switch chip behaviour, specifically: * accessing switch register space; * accessing per-PHY registers (for switches that actually expose PHYs); * basic vlan group support, which applies for the rtl8366 driver but not for the atheros switches. This also includes initial support for: * rtl8366rb support - which is a 10/100/1000 switch which supports vlan groups; * Initial Atheros AR8316 switch support - which is a 10/100/1000 switch which supports an alternate vlan configuration (so the vlan group methods are stubbed.) The general idea here is that the switch driver may speak to a variety of backend busses (mdio, i2c, spi, whatever) and expose: * If applicable, one or more MDIO busses which ethernet interfaces can then attach PHYs to via miiproxy/mdioproxy; * exposes miibusses, one for each port at the moment, so .. * .. a PHY can be exposed on each miibus, for each switch port, with all of the existing MII/ifnet framework. However: * The ifnet is manually created for now, and it isn't linked into the interface list, nor can you (currently) send/receive frames on this ifnet. At some point in the future there may be _some_ support for this, for switches with a multi-port, isolated mode. * I'm still in the process of sorting out correct(er) locking. TODO: * ray's switch code in zrouter (zrouter.org) includes a much more developed newbus API that covers the various switch methods, as well as a capability API so drivers, the switch layer and the userland utility can properly control the subset of supported features. The plan is to sort that out later, once the rest of ray's switch drivers are brought over and extended to export MII busses and PHYs. Submitted by: Stefan Bethke <stb@lassitu.de> Reviewed by: ray
* Bring over the first part of the etherswitch framework - an MDIO bus andadrian2012-05-015-0/+657
MDIO/MII rendezvous proxy. * Add an 'mdio' bus, which is the "IO" side of an MII bus (but by design can be anything which implements the underlying register access API.) * Add 'miiproxy' and 'mdioproxy', which provides a rendezvous mechanism for MII busses to appear hanging off arbitrary busses (ie, that aren't necessarily a traditional looking MII bus.) MII busses can now hang off anything that implements an mdiobus. For the AR71xx SoC, there's one MDIO bus but two MII busses. So to properly support two or more real PHYs, this can be done: # arge0 MDIO bus - there's no arge1 MDIO bus for AR71xx hint.argemdio.0.at="nexus0" hint.argemdio.0.maddr=0x19000000 hint.argemdio.0.msize=0x1000 hint.argemdio.0.order=0 # Create two mdioproxy instances hint.mdioproxy.0.at="mdio0" hint.mdioproxy.1.at="mdio0" # .. and with a follow-up patch hint.arge.0.mdio=mdioproxy0 hint.arge.1.mdio=mdioproxy0 TODO: * Do a sweep or two and add appropriate locking in mdio/mdioproxy/miiproxy. Submitted by: Stefan Bethke <stb@lassitu.de> Reviewed by: ray
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