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path: root/sys/dev/drm/i915_drv.h
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* Do not define bool/true/false if the symbols already exist.mdf2011-12-121-1/+1
| | | | | MFC after: 2 weeks Sponsored by: Isilon Systems, LLC
* Fix build after typo.rnoland2010-03-131-1/+1
| | | | | Reported by: Sergey V. Dyatko <sergey.dyatko@gmail.com> MFC after: 3 days
* Add support for Intel Pineview chips, aka IGDrnoland2010-03-131-2/+8
| | | | | | | | Slightly modified version of the submitted patch. PR: 143427 Submitted by: Mamoru Sumida <msumida@mvc.biglobe.ne.jp> MFC after: 3 days
* Import simple drm memory manager.rnoland2010-01-311-2/+2
| | | | | | | This is required for the VIA driver and at least some parts are needed for GEM. MFC after: 2 weeks
* Add support for Intel G41 chipsetrnoland2009-10-111-1/+3
| | | | | Submitted by: Artyom Mirgorodsky <man@email.com.ua> MFC after: 3 days
* Some more cleanups for vblank code on Intel.rnoland2009-06-251-1/+0
| | | | | | | | | The Intel 2d driver calls modeset before reinstalling the handler on a vt switch. This means that vblank status ends up getting cleared after it has been setup. Restore saved values for the pipestat registers rather than just wiping them out. MFC after: 3 days
* The G45 docs indicate that all G4X chips use the new framecount register.rnoland2009-06-201-1/+1
| | | | | | | | | Intel agrees with my reading of the docs, make it so for all G4X chips. The new register also has a 32 bit width as opposed to 24 bits. Fix things up so that the counters roll over properly. MFC after: 3 days
* Pull in some suspend / resume changes from Intel's codernoland2009-03-191-2/+5
| | | | | Tested by: mav@ MFC after: 3 days
* Initialize the vblank structures at load time. Previously we did thisrnoland2009-02-281-0/+2
| | | | | | | | | | | | at irq install/uninstall time, but when we vt switch, we uninstall the irq handler. When the irq handler is reinstalled, the modeset ioctl happens first. The modeset ioctl is supposed to tell us that we can disable vblank interrupts if there are no active consumers. This will fail after a vt switch until another modeset ioctl is called via dpms or xrandr. Leading to cases where either interrupts are on and can't be disabled, or worse, no interrupts at all. MFC after: 2 weeks
* The GM45 handles vblank differently. Pull the changes from Intel in.rnoland2009-02-251-0/+1
| | | | MFC after: 2 Weeks
* This was part of a sync to the code that Intel is shipping in linux.rnoland2009-02-251-1541/+85
| | | | | | | | - Remove the old TTM interface - Move register definitions to i915_reg.h - Overhaul the irq handler MFC after: 2 weeks
* The vblank_swap ioctl was fundamentally race prone. Get rid of it.rnoland2009-02-251-3/+0
| | | | MFC after: 2 weeks
* resync to git masterrnoland2008-10-031-28/+299
| | | | | | | | | | | | | | | | | | | | | | This reverts a private patch which is causing issues with many Intel chipsets. I will review that patch and see what we need to do to fix it up later, but for the time being, we will just get these chips working again. This update contains a lot of code cleanup and is post gem merge (no, we don't have gem support). It should prove much easier to read the code now. A lot of thanks goes to vehemens for that work. I have adapted the code to use cdevpriv for tracking per open file data. That alleviates the old ugly hack that we used to try and accomplish the task and helped to clean up the open / close behavior a good bit. This also replaces the hack that was put in place a year or so ago to prevent radeons from locking up with AIGLX enabled. I have had a couple of radeon testers report that it still works as expected, though I no longer have radeon hardware to test with myself. Other various fixes from the linux crew and Intel, many of which are muddled in with the gem merge. Approved by: jhb (mentor) Obtained from: mesa/drm git master MFC after: 2 weeks
* Update drm kernel drivers.rnoland2008-08-231-102/+1677
| | | | | | | | | | This is a sync to mesa/drm pre-gem, with a few fixes on top of that. It also contains one local patch supplied by kib@ that I can't apply to git.master shared code. Approved by: flz Obtained from: mesa/drm git.master MFC after: 2 weeks
* Merge from DRM upstream:anholt2006-09-071-7/+13
| | | | | | | - Add support for Intel 965 Express chipsets. - Add support for R200 vertex programs, along with minor bugfixes. - Add support for vblank synchronization to pipe B of Intel hardware (laptop screens).
* Update to DRM CVS as of 2006-04-09. The most notable new feature is the updatedanholt2006-04-091-2/+8
| | | | | | | Radeon memmap code, which with a new DDX driver and DRI drivers should fix long-term stability issues with Radeons. Also adds support for r200's ATI_fragment_shader, r300 texrect support and texture caching fixes, i915 vblank support and bugfixes, and new PCI IDs.
* Update DRM to CVS snapshot as of 2005-11-28. Notable changes:anholt2005-11-281-9/+38
| | | | | | | | | | | | | - S3 Savage driver ported. - Added support for ATI_fragment_shader registers for r200. - Improved r300 support, needed for latest r300 DRI driver. - (possibly) r300 PCIE support, needs X.Org server from CVS. - Added support for PCI Matrox cards. - Software fallbacks fixed for Rage 128, which used to render badly or hang. - Some issues reported by WITNESS are fixed. - i915 module Makefile added, as the driver may now be working, but is untested. - Added scripts for copying and preprocessing DRM CVS for inclusion in the kernel. Thanks to Daniel Stone for getting me started on that.
* Update to DRM CVS as of 2005-04-12, bringing many changes:anholt2005-04-161-0/+239
- Split core DRM routines back into their own module, rather than using the nasty templated system like before. - Development-class R300 support in radeon driver (requires userland pieces, of course). - Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others. - i915 driver files, which just need to get drm_drv.c fixed to allow attachment to the drmsub device. Covers i830 through i915 integrated graphics. - savage driver files, which should require minimal changes to work. Covers the Savage3D, Savage IX/MX, Savage 4, ProSavage. - Support for color and texture tiling and HyperZ features of Radeon. Thanks to: scottl (much p4 handholding) Jung-uk Kim (helpful prodding) PR: [1] kern/76879, [2] kern/72548 Submitted by: [1] Alex, lesha at intercaf dot ru [2] Shaun Jurrens, shaun at shamz dot net
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