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* Use proper interface for FDT parsing and memory mapping in CESAzbb2016-06-031-1/+1
| | | | | | | | | | Improvements after r301220. Bus space methods are not called so simple pmap_mapdev will suffice. Use OF_getencprop to get buffer with already converted endianess. Pointed out by: ian Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf
* Add HMAC-SHA256 support in CESAzbb2016-06-021-4/+12
| | | | | | | | | | | Only HMAC-SHA256 is added as it is the only SHA-2 variant supported by cryptodev. It is not possible to register hardware support for other algorithms in the family including regular non-keyed SHA256. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D6219
* Truncate HMAC output only if requested by the clientzbb2016-06-021-3/+5
| | | | | | | | | | | | The output of HMAC was previously truncated to 12 bytes. This was only correct in case of one particular crypto client - the new version of IPSEC. Fix by taking into account the cri_mlen field in cryptoini session request filled in by the client. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D6218
* Split CESA memory resource into TDMA and CESA regszbb2016-06-021-13/+24
| | | | | | | | | | | | | | | | TDMA and CESA registers are placed in different ranges of memory. Split memory resource in DTS to reflect that. This change is needed to support multiple CESA nodes as otherwise the ranges of different nodes would overlap. In consequence, CESA_WRITE and CESA_READ macros have been split depending on which range of registers is accessed. Offsets for CESA registers have been modified as the base address has changed. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D6217
* Map CESA SRAM memory in driver attach for Armada38xzbb2016-06-021-1/+3
| | | | | | | | | | | | | | | On other platforms with CESA accelerator the SRAM memory is mapped in early init before driver is attached. This method only works correctly with mappings no smaller than L1 section size (1MB). There may be more SRAM blocks and they may have smaller sizes than 1MB as is the case for Armada38x. Instead, map SRAM memory with bus_space_map() in CESA driver attach. Note that we can no longer assume that VA == PA for the SRAM. Submitted by: Michal Stanek <mst@semihalf.com Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D6215
* Similar to the (1 << 31) case it is not defined to do (2 << 30).eadler2013-11-301-2/+2
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* Move initialization of CESA decoding windows from common sectiongber2013-05-061-0/+5
| | | | | | | | | | | | to driver specific files. - window initialization is done during device attach - CESA TDMA decoding windows values are set based on DTS, not copied from CPU registers - remove unnecessary virtual mapping - update dts file Obtained from: Semihalf
* Initial version of cesa(4) driver for Marvell crypto engine and securityraj2011-11-191-0/+350
accelerator. The following algorithms and schemes are supported: - 3DES, AES, DES - MD5, SHA1 Obtained from: Semihalf Written by: Piotr Ziecik
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