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* Migrate the ath_hal_filltxdesc() API to take a list of buffer/seglen values.adrian2012-08-052-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing API only exposes 'seglen' (the current buffer (segment) length) with the data buffer pointer set in 'ds_data'. This is fine for the legacy DMA engine but it won't work for the EDMA engines. The EDMA engine has a significantly different TX descriptor layout. * The legacy DMA engine had a ds_data pointer at the same offset in the descriptor for both TX and RX buffers; * The EDMA engine has no ds_data for RX - the data is DMAed after the descriptor; * The EDMA engine has support for 4 TX buffer/segment pairs in the TX DMA descriptor; * The EDMA TX completion is in a different FIFO, and the driver will 'link' the status completion entry to a QCU by a "QCU ID". I don't know why it's just not filled in by the hardware, alas. So given that, here are the changes: * Instead of directly fondling 'ds_data' in ath_desc, change the ath_hal_filltxdesc() to take an array of buffer pointers as well as segment len pointers; * The EDMA TX completion status wants a descriptor and queue id. This (for now) uses bf_state.bfs_txq and will extract the hardware QCU ID from that. * .. and this is ugly and wasteful; it should change to just store the QCU in the bf_state and save 3/7 bytes in the process. Now, the weird crap: * The aggregate TX path was using bf_state->bfs_txq for the TXQ, rather than taking a function argument. I've tidied that up. * The multicast queue frames get put on a software TXQ and then that is appended to the hardware CABQ when appropriate. So for now, make sure that bf_state->bfs_txq points at the CABQ when adding frames to the multicast queue. * .. but the multicast queue TX path for now doesn't use the software queue and instead (a) directly sets up the descriptor contents at that point; (b) the frames on the vap->avp_mcastq are then just appended wholesale to the CABQ. So for now, I don't have to worry about making the multicast path work with aggregation or the per-TID software queue. Phew. What's left to do: * I need to modify the 11n ath_hal_chaintxdesc() API to do the same. I'll do that in a subsequent commit. * Remove bf_state.bfs_txq entirely and store the QCU as appropriate. * .. then do the runtime "is this going on the right HWQ?" checks using that, rather than comparing pointer values. Tested on: * AR9280 STA/AP * AR5416 STA/AP
* Flesh out the multi-rate retry capability.adrian2012-07-281-0/+1
| | | | | | | | The existing method for testing for MRR is to call the "SetupXTXDesc" HAL method and see if it returns AH_TRUE or AH_FALSE. This capability explicitly lists what number of multi-rate attempts are possible. "1" means "one rate attempt supported".
* Break out the TX descriptor link field into HAL methods.adrian2012-07-193-0/+33
| | | | | | | | | | | | | | | | The DMA FIFO chips (AR93xx and later) differ slightly to th elegacy chips: * The RX DMA descriptors don't have a ds_link field; * The TX DMA descriptors have a ds_link field however at a different offset. This is a reimplementation based on what the reference driver and ath9k does. A subsequent commit will enable it in the TX and beacon paths. Obtained from: Linux ath9k, Qualcomm Atheros
* Extend the RX HAL API to include the RX queue identifier.adrian2012-07-092-4/+8
| | | | | | | | | | The AR93xx and later chips support two RX FIFO queues - a high and low priority queue. For legacy chips, just assume the queues are high priority. This is inspired by the reference driver but is a reimplementation of the API and code.
* oops - ath_hal_disablepcie is actually destined for another purpose,adrian2012-05-251-3/+4
| | | | | | | not to disable the PCIe PHY in prepration for reset. Extend the enablepci method to have a "poweroff" flag, which if equal to true means the hardware is about to go to sleep.
* Change the MIB cycle count API to return HAL_BOOL, rather than uint32_t,adrian2012-05-013-2/+15
| | | | | | | to return whether it was successful. Add placeholder (blank) methods for previous chips, for both it and the 11n extension channel busy call.
* After thinking about this a bit more, let's not keep statistics per-channeladrian2012-04-283-5/+5
| | | | | | | | | | | | | | | in the HAL. That's very memory hungry (32k just for channel statistics) which would be better served by keeping a summary in the ANI state. Or, later, keep a survey history in net80211. So: * Migrate the ah_chansurvey array to be a single entry, for the current channel. * Change the ioctl interface and ANI code to just reference that. * Clear the ah_chansurvey array during channel reset, both in the AR5212 and AR5416 reset path.
* Fetch the channel survey code from the HAL.adrian2012-04-282-0/+9
| | | | | This information is currently not being populated by any of the HAL modules.
* Stop using the hardware register value byte order swapping for now,adrian2012-04-191-4/+3
| | | | | | | | | | | | | | | at least until I can root cause what's going on. The only platform I've seen this on is the AR9220 when attached to the AR71xx CPUs. I get immediate PCIe bus errors and all subsequent accesses cause further MIPS bus exceptions. I don't have any other big-endian platforms to test this on. If I get a chance (or two), I'll try to whack this on a bus analyser and see exactly what happens. I'd rather leave this on, especially for slower, embedded platforms. But the #ifdef hell is something I'm trying to avoid.
* Radar API related fixes.adrian2012-01-303-0/+18
| | | | | | | | | | | | * For legacy NICs, the combined RSSI should be used. For earlier AR5416 NICs, use control chain 0 RSSI rather than combined RSSI. For AR5416 > version 2.1, use the combined RSSI again. * Add in a missing AR5212 HAL method (get11nextbusy) which may be called by radar code. This serves no functional change for what's currently in FreeBSD.
* Use the correct types when calling the decompression mask function.adrian2011-12-221-1/+1
| | | | | | | | | | | | There's currently no public code which uses this feature and the current reference driver doesn't enable this feature at all. It's possible it was used by a previous version of the driver and that indeed it should return HAL_STATUS; but at this point I'm happy to require that they complain and submit a patch. This was found by LLVM compile-time type checking. Submitted by: dim
* Revert r228786. We'll need to work around the warnings in another way.dim2011-12-221-1/+1
| | | | | Requested by: adrian MFC after: 1 week
* Fix enum conversion problems in sys/dev/ath/ath_hal/ar5212/ar5212_misc.cdim2011-12-211-1/+1
| | | | | | | | | | | | | | | | | | and sys/dev/ath/ath_hal/ar5416/ar5416_misc.c: sys/dev/ath/ath_hal/ar5212/ar5212_misc.c:577:24: warning: implicit conversion from enumeration type 'HAL_STATUS' to different enumeration type 'HAL_BOOL' [-Wconversion] return HAL_EINVAL; ~~~~~~ ^~~~~~~~~~ and: sys/dev/ath/ath_hal/ar5416/ar5416_misc.c:164:9: warning: implicit conversion from enumeration type 'HAL_STATUS' to different enumeration type 'HAL_BOOL' [-Wconversion] return HAL_OK; ~~~~~~ ^~~~~~ In both cases, enums HAL_BOOL and HAL_STATUS are mixed up. MFC after: 1 week
* The AR5413 datasheet specifies that AR_TxIntrReq should be set consistentlyadrian2011-10-251-2/+9
| | | | for all frames, so do so.
* Save and restore the association ID across interface resets.adrian2011-10-253-3/+6
| | | | | Obtained from: Atheros MFC after: 1 week
* Port over some missing code from the ar5212 reference driver reset path.adrian2011-10-182-2/+147
| | | | | | | | The final missing bit here is enabling the PCI configuration register read, but there's currently no glue available for the HAL to read (and write) PCI configuration space registers. Obtained from: Atheros
* Fix a corner case in the HAL debugging changes, where ah was NULL.adrian2011-09-302-3/+3
| | | | | | | | | | | | | Although I tried to fix this earlier by introducing HALDEBUG_G(), it turns out there seem to be other cases where the pointer value is still NULL. * Fix DO_HALDEBUG() and the HALDEBUG macro to check whether ah is NULL before deferencing it * Remove HALDEBUG_G() as it's no longer needed This is hopefully a merge candidate for 9.0-RELEASE as enabling debugging at startup could result in a kernel panic.
* Change the default CABQ time to be 70% of the beacon interval,adrian2011-09-281-6/+31
| | | | | | | | | | | | | | | rather than the whole beacon interval. The reference driver and Linux ath9k both choose 80% of the beacon interval and they do it in the driver rather than the HAL (Ath reference) or ath9k_hw (ath9k.) This quietens stuck beacon conditions on my AR9220/AR9280 based NICs when a lot of burst broadcast/multicast traffic is going on. It doesn't seem to annoy the earlier MACs as much as the AR9280 and later one. Obtained from: Linux ath9k, Atheros
* The AR5212 setup path (also used by the AR5416 code) configures aadrian2011-09-281-0/+2
| | | | | | | | | | | | | | | | | | local variable with a beacon interval of 100 TU. This never gets modified if the beacon interval configuration changes. This may have been correct in earlier times, but with the advent of staggered beacons (which default to 1 / ATH_BCBUF beacon interval, so 25 TU here) this value is incorrect. It is used to configure the default CABQ readytime. So here, the cabq was being configured to be much greater than the target beacon timer (TBTT.) The driver should be configuring a cabq readytime value rather then leaving it to the HAL to choose sensible defaults. This should be done in the future - I'm simply trying to ensure sensible defaults are chosen.
* Update the TSF and next-TBTT methods to work for the AR5416 and later NICs.adrian2011-09-083-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is another commit in a series of TDMA support fixes for the 11n NICs. * Move ath_hal_getnexttbtt() into the HAL; write methods for it. This returns a timer value in TSF, rather than TU. * Move ath_hal_getcca() and ath_hal_setcca() into the HAL too, where they likely now belong. * Create a new HAL capability: HAL_CAP_LONG_RXDESC_TSF. The pre-11n NICs write 15 bit TSF snapshots into the RX descriptor; the AR5416 and later write 32 bit TSF snapshots into the RX descriptor. * Use the new capability to choose between 15 and 31 bit TSF adjustment functions in ath_extend_tsf(). * Write ar5416GetTsf64() and ar5416SetTsf64() methods. ar5416GetTsf64() tries to compensate for TSF changes at the 32 bit boundary. According to yin, this fixes the TDMA beaconing on 11n chipsets and TDMA stations can now associate/talk, but there are still issues with traffic stability which need to be investigated. The ath_hal_extendtsf() function is also used in RX packet timestamping; this may improve adhoc mode on the 11n chipsets. It also will affect the timestamps seen in radiotap frames. Submitted by: Kang Yin Su <cantona@cantona.net> Approved by: re (kib)
* Add another HAL method - ah_isFastClockEnabled - which returns AH_TRUEadrian2011-08-083-0/+12
| | | | | | | | | | | if 5ghz fast clock is enabled in the current operating mode. It's slightly dirty, but it's part of the reference HAL and used by the (currently closed-source) radar event code to map radar pulses back to microsecond durations. Obtained from: Atheros Approved by: re (kib, blanket)
* Fix ANI handling to work correctly when (trying) to receive radar errors.adrian2011-07-301-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | * Teach the AR5212/AR5416 ANI code to use the RX filter methods, rather than calling the RX filter routines directly. * Make HAL_ANI_PRESENT and HAL_ANI_MODE unconditionally available, regardless of whether ah_ani_function is masking it. * (Mostly) fully disable ANI if interference mitigation is disabled. When disabled, the ANI code doesn't touch any ANI/PHY registers, leaving them the default value. This is in line with what the Atheros reference driver does. * Correctly set the ANI parameters during ANI reset, rather than when ANI is enabled. In this way, if ANI is disabled or enabled whilst the NIC is not active (and there's no current channel), bogus parameters or a NULL pointer deference doesn't occur. There's still some lingering issues - notably, the MIB events/interrupts aren't fully disabled, so MIB interrupts still occur. I'll worry about that later. Approved by: re (kib)
* Re-introduce a global ath_hal_debug again for now, whilst I figure out whatadrian2011-06-232-3/+3
| | | | | | | | | | | | to do about the few cases where the HAL state isn't available (regdomain) or isn't yet setup (probe/attach.) The global ath_hal_debug now affects all instances of the HAL. This also restores the ability for probe/attach debugging to work; as the sysctl tree may not be attached at that point. Users can just set the global "hw.ath.hal.debug" to a suitable value to enable probe/attach related debugging.
* Fix indenting issues introduced by the previous commit.adrian2011-06-231-2/+2
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* Break out most of the HAL related tweaks into a per-HAL instance,adrian2011-06-232-5/+5
| | | | | | | | | | | | | | | | | rather than global variables. This specifically allows for debugging to be enabled per-NIC, rather than globally. Since the ath driver doesn't know about AH_DEBUG, and to keep the ABI consistent regardless of whether AH_DEBUG is enabled or not, enable the debug parameter always but only conditionally compile in the debug methods if needed. The ALQ support is currently still global pending some brainstorming. Submitted by: ssgriffonuser@gmail.com Reviewed by: adrian, bschmidt
* Since HAL_PHYERR_* is used in the radar code, always include ah_desc.h.adrian2011-06-071-2/+0
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* Flesh out a new HAL method to fetch the radar PHY error frame information.adrian2011-06-073-0/+48
| | | | | | | | | | | | | | | | | | | | | | | For the AR5211/AR5212, this is apparently a one byte pulse duration counter value. It is only coded up here for the AR5212 as I don't have any AR5211-series hardware to test it on. This information was extracted from the Madwifi DFS branch along with some local additions. Please note - all this does is extract out the radar event duration, it in no way reflects the presence of a radar. Further code is needed to take a set of radar events and filter them to extract out correct radar pulse trains (and ignore other events.) For further information, please see: http://wiki.freebsd.org/dev/ath_hal%284%29/RadarDetection This includes references to the relevant patents which describe what is going on. Obtained from: Madwifi
* Bring over the relevant registers to use when implementing the quiet timeadrian2011-06-034-0/+18
| | | | | | | | | portion of 802.11h. The AR5212 code has been brought over as a reference, it's currently untested. Obtained from: Atheros
* Add some missing DFS chipset functionality to the FreeBSD HAL.adrian2011-06-013-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | Please note - this doesn't in any way constitute a full DFS implementation, it merely adds the relevant capability bits and radar detection threshold register access. The particulars: * Add new capability bits outlining what the DFS capabilities are of the various chipsets. * Add HAL methods to set and get the radar related register values. * Add AR5212 and AR5416+ DFS radar related register value routines. * Add a missing HAL phy error code that's related to radar event processing. * Add HAL_PHYERR_PARAM, a data type that encapsulates the radar register values. The AR5212 routines are just for completeness. The AR5416 routines are a super-set of those; I may later on do a drive-by pass to tidy up duplicate code. Obtained from: Linux, Atheros
* The current ANI capability information uses a different set ofadrian2011-05-251-7/+9
| | | | | | | | | | | | | | | | values for the commands, compared to the internal command values (HAL_ANI_CMD.) My eventual aim is to make the HAL_ANI_CMD internal enum match the public API and then remove all this messiness. This now allows HAL_CAP_INTMIT users to use a public HAL_CAP_INTMIT_ enum rather than magic constants. The only magic constants currently used by if_ath are "enable" and "present". Some local tools of mine allow for direct, manual fiddling of the ANI variables and I'll convert these to use the public enum API before I commit them.
* The ANI control for the AR5416 and later chips was calling ar5212AniControl(),adrian2011-05-243-2/+8
| | | | | | | | | | which did AR5212 specific initialisation. This would cause some slight silliness when enabling/disabling ANI. Just to be completely correct - and to ensure the phy error mask/RX filter register isn't incorrectly played with - make the ANI control function a method, have it set appropriately for AR5212/AR5416, and call that from the ANI control interface.
* Fix case, introduced in my previous commit.adrian2011-05-171-1/+1
| | | | | Pointy hat goes to: adrian, for having multiple build screens open and checking the wrong one.
* Use the halMcastKeySrchSupport capability bit to selectively enable/disableadrian2011-05-171-1/+1
| | | | | | | | | the multicast key search support for AR5212, AR5416 and later. The general HAL routine ath_hal_getcapability() implement checking this but it's overridden by a check in ar5212_misc:ar5212GetCapability(). This restores the later functionality in case it's found to be broken in any of the 11n chipsets.
* Add some more OS_MARK probes to the RX DMA setup/teardown code path.adrian2011-04-071-0/+4
| | | | | I'm trying to debug the RX DMA path and help the ath9k guys with "RX dma abort stuck" issue that both our drivers have.
* Add a HAL capability bit for supporting self-linked RX descriptors and ↵adrian2011-04-041-0/+1
| | | | | | | | | | | | | | | | | | | disable it for the 11n chipsets. From the ath9k source: == 11N: we can no longer afford to self link the last descriptor. MAC acknowledges BA status as long as it copies frames to host buffer (or rx fifo). This can incorrectly acknowledge packets to a sender if last desc is self-linked. == Since this is useful for pre-AR5416 chips that communicate PHY errors via error frames rather than by on-chip counters, leave the support in there, but disable it for AR5416 and later.
* Make sure that the AR_MISC_MODE value from the initvals are properly respected.adrian2011-03-192-2/+2
| | | | | | | | | | | | | | | | | | | | | This commit really is "fix the OFDM duration calculation to match reality when running in 802.11g mode." The AR5212 init vals set AR_MISC_MODE to 0x0 and all the bits that can be set are set through code. The AR5416 and later initvals set AR_MISC_MODE to various other values (with the AR5212 AR_MISC_MODE options cleared), which include AR_PCU_CCK_SIFS_MODE . This adds 6uS to SIFS on non-CCK frames when transmitting. This fixes the issue where _DATA_ 802.11g OFDM frames were being TX'ed with the ACK duration set to 38uS, not 44uS as on the AR5212 (and other devices.) The AR5212 TX pathway obeys the software-programmed duration field in the packet, but the 11n TX pathway overrides that with a hardware-calculated duration. This was getting it wrong because of the above AR_MISC_MODE setting. I've verified that 11g data OFDM frames are now being TXed with the correct ACK+SIFS duration programmed in.
* For chips that are full reset in ar5416ChipReset(), save and restore the TSF.adrian2011-03-092-0/+8
| | | | | | | Merlin (ar9280) and later were full-reset if they're doing open-loop TX power control but the TSF wasn't being saved/restored. Add ar5212SetTsf64() which sets the 64 bit TSF appropriately.
* Fix the keycache behaviour for multicast keycache search.adrian2011-02-091-1/+18
| | | | | | | | | | | | | | | The correct bit to set is 0x1 in the high MAC address byte, not 0x80. The hardware isn't programmed with that bit (which is the multicast adress bit.) The linux ath9k keycache code uses that bit in the MAC as a "this is a multicast key!" and doesn't set the AR_KEYTABLE_VALID bit. This tells the hardware the MAC isn't to be used for unicast destination matching but it can be used for multicast bssid traffic. This fixes some encryption problems in station mode. PR: kern/154598
* There's apparently a bug with Merlin (AR9280) and later chipsets whereadrian2011-02-081-0/+2
| | | | | | | | | | | | putting descriptors (not buffers) across a 4k page boundary can cause issues. I've not seen it in production myself but it apparently can cause problems. So, in preparation for addressing this workaround, (re)-expose the particular HAL capability bit which marks whether the chipset has support for cross-4k- boundary transactions or not. A subsequent commit will modify the descriptor allocation to avoid allocating descriptor entries that straddle a 4k page boundary.
* Fix typo in SIFS setupadrian2011-02-071-1/+1
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* Make space for the extended 802.11n MCS rate tables.adrian2011-01-281-1/+1
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* ANI changes #1 - split out the ANI polling from the RxMonitor hook.adrian2011-01-213-6/+13
| | | | | | | | | | The rxmonitor hook is called on each received packet. This can get very, very busy as the tx/rx/chanbusy registers are thus read each time a packet is received. Instead, shuffle out the true per-packet processing which is needed and move the rest of the ANI processing into a periodic event which runs every 100ms by default.
* Include the initial support for external EEPROMs.adrian2011-01-201-1/+2
| | | | | | | | | | | | | | The AR9100 at least doesn't have an external serial EEPROM attached to the MAC; it instead stores the calibration data in the normal system flash. I believe earlier parts can do something similar but I haven't experienced it first-hand. This commit introduces an eepromdata pointer into the API but doesn't at all commit to using it. A future commit will include the glue needed to allow the AR9100 support code to use this data pointer as the EEPROM.
* Add a new HAL method to retrieve the completion schedule. It setsadrian2011-01-203-0/+24
| | | | | | | | | | | the completion schedule from the hardware and returns AH_TRUE if the hardware supports multi-rate retries (AR5212 and above); and returns AH_FALSE if the hardware doesn't support multi-rate retries. The sample rate module directly reads the TX completion descriptor and extracts the TX schedule information from that. It will be updated in a future commit to instead use this method to determine the completion schedule.
* Add a couple of functions to check NF calibration progress / completion.adrian2010-08-122-0/+39
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* The Atheros AR71xx CPUs, when paired with the AR5212 parts, has a bugimp2010-05-011-0/+8
| | | | | | | | | | | | | | | | | | | that generates a fatal bus trap. Normally, the chips are setup to do 128 byte DMA bursts, but when on this CPU, they can only safely due 4-byte DMA bursts due to this bug. Details of the exact nature of the bug are sketchy, but some can be found at https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and 6. There's a small performance penalty associated with this workaround, so it is only enabled when needed on the Atheros AR71xx platforms. Unfortunately, this condition is impossible to detect at runtime without MIPS specific ifdefs. Rather than cast an overly-broad net like Linux/OpenWRT dues (which enables this workaround all the time on MIPS32 platforms), we put this option in the kernel for just the affected machines. Sam didn't like this aspect of the patch when he reviewed it, and I'd love to hear sane proposals on how to fix it :) Reviewed by: sam@
* Introduce ath_hal_setInterrupts(), a macro for ah_setInterrupts().rpaulo2010-03-031-2/+2
| | | | Pointed out by: sam
* Replace Id keyword with FreeBSD keyword and set the svn props correctly.rpaulo2010-03-037-7/+7
| | | | No functional change.
* Couple of suggestions from Sam regarding latest commit:rpaulo2010-03-023-7/+9
| | | | | | | o rename the new variables to comply with the naming scheme o move the new variables to an AR5212 specific struct o use ahp when available o revert to previous ts_flags check
* Properly setup the TX FIFO threshold for AR5416 based chipsets,rpaulo2010-03-012-3/+12
| | | | | | including the AR9285. This seems to fix some users's problems. Submitted by: Jorge Boncompte [DTI2] <jorge at dti2.net>
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