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* Add missing bus_dmamap_sync() calls for the work DMA map.marius2011-03-061-1/+14
| | | | MFC after: 2 weeks
* Add missing bus_dmamap_sync() calls for the work DMA map.marius2011-03-061-1/+17
| | | | MFC after: 2 weeks
* - Allocate the DMA memory used for the work area as coherent as at leastmarius2011-03-061-3/+4
| | | | | | | | the ataahci(4) and atamarvell(4) drivers share it between the host and the controller. - Spell some zeros as BUS_DMA_WAITOK when used as bus_dmamem_alloc() flags. MFC after: 2 weeks
* Add the disk ident and a human-meaningful description (here, the disk modelnwhitehorn2011-02-261-0/+2
| | | | | | | string) to the geom_disk config XML so that they are easily accessible from userland. MFC after: 1 week
* Support for the new Patsburg PCH chipset:jfv2011-02-012-0/+11
| | | | | | | | | | | - SMBus Controller - SATA Controller - HD Audio Controller - Watchdog Controller Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code. MFC after 3 days
* Support for the new DH89xxCC PCH chipset including:jfv2011-01-312-0/+2
| | | | | | - SATA controller - Watchdog timer - SMBus controller
* ICH7 SATA controller in legacy mode can provide access to SATA registersmav2011-01-241-14/+104
| | | | | | | | via AHCI-like memory resource at BAR(5). Use it if BIOS was so kind to allocate memory for that BAR. This allows hot-plug support and connection speed reporting. MFC after: 2 weeks
* Several chipset drivers alter parameters relevant for the DMA tag creation,marius2010-11-288-28/+33
| | | | | | | | | | | | i.e. alignment, max_address, max_iosize and segsize (only max_address is thought to have an negative impact regarding this issue though), after calling ata_dmainit() either directly or indirectly so these values have no effect or at least no effect on the DMA tags and the defaults are used for the latter instead. So change the drivers to set these parameters up-front and ata_dmainit() to honor them. Reviewd by: mav MFC after: 1 month
* Do hard reset before soft reset for SATA channels. Soft reset reported to bemav2010-11-271-1/+1
| | | | | | not enough to restore device readiness in some situations. Tested by: Roger Hammerstein <cheeky.m@live.com> on ServerWorks HT1000.
* Make ATA_CAM wrapper to report SATA power management capabilities to CAM tomav2010-11-182-0/+20
| | | | | make it configure device to initiate transitions if controller configured to accept them. This makes hint.ata.X.pm_level=1 mode working.
* Even if we are skipping SATA hard reset - set power management bits inmav2010-11-181-1/+5
| | | | | SControl register. This should make things consistent and help to avoid unexpected PHY events that I've noticed in some cases on VIA controllers.
* Record that there is no devices if SATA reset found none.mav2010-11-181-0/+2
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* Some VIA SATA controllers provide access to non-standard SATA registers viamav2010-11-181-4/+128
| | | | | PCI config space. Use them to implement hot-plug and link speed reporting. Tested on ASRock PV530 board with VX900 chipset.
* Add IDs for VIA VX900 chipset SATA controller.mav2010-11-171-0/+3
| | | | (Missed part of r215428)
* Add IDs for VIA VX900 chipset SATA controller.mav2010-11-171-1/+4
| | | | MFC after: 1 week
* Fix typos.brucec2010-11-091-4/+4
| | | | | PR: bin/148894 Submitted by: olgeni
* Teach ahci(4), siis(4) and ATA_CAM ata(4) wrapper report to CAM residualmav2010-11-081-0/+9
| | | | I/O length on underruns, that often happens for some SCSI commands.
* Mark command submission timeouts as timeouts. This should trigger devicemav2010-11-061-8/+13
| | | | resets and increase chances of getting device back again.
* Add support for odd-sized PIO transfers, sometimes used by ATAPI.mav2010-11-061-6/+18
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* Remove stale line, accidentally slipped into r214016.mav2010-11-021-1/+0
| | | | MFC after: 3 days
* Set of legacy mode SATA enchancements:mav2010-10-1811-158/+511
| | | | | | | | | | | | - Implement proper combined mode decoding for Intel controllers to properly identify SATA and PATA channels and associate ATA channels with SATA ports. This fixes wrong reporting and in some cases hard resets to wrong SATA ports. - Improve SATA registers support to handle hot-plug events and potentially interface errors. For ICH5/6300ESB chipsets these registers accessible via PCI config space. For later ones they may be accessible via PCI BAR(5). - For controllers not generating interrupts on hot-plug events, implement periodic status polling. Use it to detect hot-plug on Intel and VIA controllers. Same probably could also be used for Serverworks and SIS.
* Revert r132291.mav2010-09-301-2/+1
| | | | | Restore setting PIO/WDMA timings for VIA UDMA133 controllers. Linux disables only AST register writing there, but no all timings.
* Add missing le32toh(), same as recently done in ata-siliconimage.c.mav2010-09-241-1/+1
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* Add missing byteswap, works on big endian systems now (tested on Netlogicjchandra2010-09-231-1/+1
| | | | | | | XLS MIPS processor). Submitted by: Sreekanth M. S. <kanthms at netlogicmicro dot com> Reviewed by: mav
* Fix a problem where device detection would work unreliably on Serverworksnwhitehorn2010-09-093-20/+34
| | | | | | | | | | | | K2 SATA controllers. The chip's status register must be read first, and as a long, for other registers to be correctly updated after a command, and this includes the command sequence in device detection as well as the previously handled case after interrupts. While here, clean up some previous hacks related to this controller. Reported by: many Reviewed by: mav MFC after: 3 weeks
* Add fix for SiI3114 and SiI3512 chips bug, which caused sending R_ERR inmav2010-09-021-0/+8
| | | | | | | | response to DMA activate FIS under certain circumstances. This is recommended fix from chip datasheet. If triggered, this bug most likely cause write command timeout. MFC after: 2 weeks
* SATA1.x SiliconImage controllers on power-on reset TFD Status register intomav2010-09-023-17/+15
| | | | | | | value 0xff. On hot-plug this value confuses ata_generic_reset() device presence detection logic. As soon as we already know drive presence from SATA hard reset, hint ata_generic_reset() to wait for device signature until success or full timeout.
* Increase device reset timeout from 10 to 15 seconds, same as in ahci(4).mav2010-09-011-1/+1
| | | | Some devices found need about 10-12 seconds to spinup.
* Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existingmav2010-08-282-16/+43
| | | | | | | entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers. Submitted by: jfv@ MFC after: 1 week
* Export PCI IDs of ATA/SATA controllers through CAM and ata(4) layers tomav2010-07-252-1/+23
| | | | | GEOM. This information needed for proper soft-RAID's on-disk metadata reading and writing.
* Make legacy ATA emulation detection more strict. This should fix falsemav2010-07-161-1/+2
| | | | | | | positive legacy detection and attach failure/panic for Marvell 88SX6141 controller and potentially some others. PR: kern/145064
* Improve interrupt setup errors handling.mav2010-07-161-1/+7
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* Disable multi-sector PIO transfers if ATA_SET_MULTI command failed.mav2010-07-131-0/+2
| | | | Submitted by: Mikolaj Golub on fs@
* Revert and remake r209883:mav2010-07-121-9/+15
| | | | | | | | | | Do not grab lock while setting up interrupt, as it causes LOR with allocation code. Instead make interrupt handler check that CAM bus initialization completed before touching it. While there, slightly improve attach errors handling. Reported by: kib
* If ata_sata_phy_reset() failed and ata_generic_reset() is not called, markmav2010-07-107-1/+24
| | | | | channel as having no devices connected. This improves hot-unplug operation on legacy-emulating SATA controllers.
* On attach, grab channel lock before setting up interrupt. This fixes crashmav2010-07-101-3/+5
| | | | | in ATA_CAM mode if phy connect event arrive before CAM bus initialization completed.
* Make hw.ata.ata_dma_check_80pin tunable affect not only device side, butmav2010-07-1011-15/+22
| | | | | | also controller side cable checks. Make respective sysctl writable. PR: kern/143462
* Add a safety-belt. If the identified disk has 0 blocks, don't attachimp2010-07-041-3/+8
| | | | | | | it. This can happen in some cases when plugging in SD/SmartCard PC Cards with empty slots. It is better to detect this bogosity, and refuse to attach rather than panic with a division by zero (in one of many places) down stream.
* Minor formatting nits.imp2010-07-041-2/+2
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* Add ata(4) ability to limit initial ATA mode for devices via device hints.mav2010-07-032-2/+56
| | | | | | | After boot this mode can be changed with atacontrol/camcontrol as usual. It works for both legacy and ATA_CAM wrapper mode. PR: kern/123980
* Following r209299, level interrupts are low by default on PPC, so removenwhitehorn2010-06-181-7/+0
| | | | the hack here to reprogram the interrupt for K2 SATA devices.
* Some revisions of the Serverworks K2 SATA controller have a datanwhitehorn2010-06-063-1/+21
| | | | | | | | | | | | | | corruption bug where if an ATA command is issued before DMA is started, data will become available to the controller before it knows what to do with it. This results in either data corruption or a controller crash. This patch remedies the problem by adopting the workaround employed by Linux and Darwin: starting the DMA engine prior to sending the ATA command. Observer on: Xserve G5 Reviewed by: mav MFC after: 1 week
* Correct the comment. We now use level low instead of edge high for thisnwhitehorn2010-06-051-1/+1
| | | | interrupt.
* Partially revert r208162 while waiting for review on a more comprehensivenwhitehorn2010-06-051-0/+7
| | | | | | | | | | | | fix. On Apple OpenPICs, the low/high bit of the interrupt sense is only respected for interrupt 0. We currently erroneously program all OpenPIC interrupts level high instead of level low by default, which only matters for some G5 systems where the SATA controllers use IRQ 0. This change is a quick fix that will be reverted once the effect of changing the default interrupt sense on embedded systems is known. MFC after: 3 days
* Fix possible use after free.mav2010-06-051-2/+2
| | | | | Found with: Coverity Prevent(tm) CID: 4634
* Fix use after free on error.mav2010-06-051-0/+1
| | | | | Found with: Coverity Prevent(tm) CID: 4722
* Fix PCH chipset IDs. They are 0x3bxx, not 0x3axx.mav2010-06-041-16/+16
| | | | Pointy hat to: me
* Report ATA/SATA channel number to NewBus at location string.mav2010-05-222-0/+14
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* Improve suspend/resume support. Make sure controller is idle on suspendmav2010-05-211-4/+15
| | | | and reset it on resume.
* Change ad_firmware_geom_adjust() to operate on a struct disk * only andmarius2010-05-201-3/+3
| | | | | | | | | hook it up to ada(4) also. While at it, rename *ad_firmware_geom_adjust() to *ata_disk_firmware_geom_adjust() etc now that these are no longer limited to ad(4). Reviewed by: mav MFC after: 3 days
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