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* Fix multicast handling. All Atheros controllers use big-endian formyongari2009-09-291-1/+1
| | | | | | in computing multicast hash. PR: kern/139137
* Disable Rx checksum offload until I find more clue why it breaksyongari2009-06-291-0/+8
| | | | | | | | | | under certain environments. However give users chance to override it when he/she surely knows his/her hardware works with Rx checksum offload. Reported by: Ulrich Spoerlein ( uqs <> spoerlein dot net ) MFC after: 1 week Approved by: re (kensmith)
* Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/rwatson2009-06-261-2/+2
| | | | | | | | | | | | | IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
* Now pci(4) handles PCIM_CMD_INTxDIS so there is no need to pokeyongari2009-03-051-10/+1
| | | | this bit in driver.
* AR8113 also need to set DMA read burst value. This should fixyongari2008-12-031-4/+2
| | | | | | occasional DMA read error seen on AR8113. Submitted by: Jie Yang < Jie.Yang <> Atheros com >
* Add some PHY magic to enable PHY hibernation and 1000baseT/10baseTyongari2008-12-031-0/+33
| | | | | | | power adjustment. This change is required to guarantee correct operation on certain switches. Submitted by: Jie Yang < Jie.Yang <> Atheros com >
* Add ale(4), a driver for Atheros AR8121/AR8113/AR8114 PCIe ethernetyongari2008-11-123-0/+4090
controller. The controller is also known as L1E(AR8121) and L2E(AR8113/AR8114). Unlike its predecessor Attansic L1, AR8121/AR8113/AR8114 uses completely different Rx logic such that it requires separate driver. Datasheet for AR81xx is not available to open source driver writers but it shares large part of Tx and PHY logic of L1. I still don't understand some part of register meaning and some MAC statistics counters but the driver seems to have no critical issues for performance and stability. The AR81xx requires copy operation to pass received frames to upper stack such that ale(4) consumes a lot of CPU cycles than that of other controller. A couple of silicon bugs also adds more CPU cycles to address the known hardware bug. However, if you have fast CPU you can still saturate the link. Currently ale(4) supports the following hardware features. - MSI. - TCP Segmentation offload. - Hardware VLAN tag insertion/stripping with checksum offload. - Tx TCP/UDP checksum offload and Rx IP/TCP/UDP checksum offload. - Tx/Rx interrupt moderation. - Hardware statistics counters. - Jumbo frame. - WOL. AR81xx PCIe ethernet controllers are mainly found on ASUS EeePC or P5Q series of ASUS motherboards. Special thanks to Jeremy Chadwick who sent the hardware to me. Without his donation writing a driver for AR81xx would never have been possible. Big thanks to all people who reported feedback or tested patches. HW donated by: koitsu Tested by: bsam, Joao Barros <joao.barros <> gmail DOT com > Jan Henrik Sylvester <me <> janh DOT de > Ivan Brawley < ivan <> brawley DOT id DOT au >, CURRENT ML
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