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* MFC r305536: Fix channel initialization in FBS mode.mav2016-09-141-15/+15
| | | | | | | Due to reading initialized variable, FIS receive area was always allocated as 256 bytes, suitable for command-based switching, instead of 4096 bytes, required for FIS-based switching. This caused memory corruption in case of port multipliers used on FBS-capable HBAs (Marvell).
* MFC r304521: JMicron JMB361 has only a single SATA portavg2016-08-231-1/+1
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* MFC r302947: In AHCI_IRQ_MODE_AFTER mode do not clear interrupts below.mav2016-08-181-0/+1
| | | | | | This is probably a NOP change since IS register is not activery used for interrupts below the shared, but it looked odd to clear interrupts we did not handle.
* MFC r302946:mav2016-08-181-1/+2
| | | | | Do not consider the last interrupt shared if there are enough interrupts for all channels.
* Fix ahci(4) driver attach to controller with 32 ports.mav2016-07-072-4/+4
| | | | | | | | | | Incorrect sign expansion in variables that supposed to be a bit fields caused infinite loop. Fixing this allows system properly detect maximal possible 32 devices configured on AHCI HBA of BHyVe. That case did not happen in a wild before due to lack of hardware AHCI HBAs with 32 ports. Approved by: re (gjb@) MFC after: 1 week
* Add support for managing Shingled Magnetic Recording (SMR) drives.ken2016-05-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change includes support for SCSI SMR drives (which conform to the Zoned Block Commands or ZBC spec) and ATA SMR drives (which conform to the Zoned ATA Command Set or ZAC spec) behind SAS expanders. This includes full management support through the GEOM BIO interface, and through a new userland utility, zonectl(8), and through camcontrol(8). This is now ready for filesystems to use to detect and manage zoned drives. (There is no work in progress that I know of to use this for ZFS or UFS, if anyone is interested, let me know and I may have some suggestions.) Also, improve ATA command passthrough and dispatch support, both via ATA and ATA passthrough over SCSI. Also, add support to camcontrol(8) for the ATA Extended Power Conditions feature set. You can now manage ATA device power states, and set various idle time thresholds for a drive to enter lower power states. Note that this change cannot be MFCed in full, because it depends on changes to the struct bio API that break compatilibity. In order to avoid breaking the stable API, only changes that don't touch or depend on the struct bio changes can be merged. For example, the camcontrol(8) changes don't depend on the new bio API, but zonectl(8) and the probe changes to the da(4) and ada(4) drivers do depend on it. Also note that the SMR changes have not yet been tested with an actual SCSI ZBC device, or a SCSI to ATA translation layer (SAT) that supports ZBC to ZAC translation. I have not yet gotten a suitable drive or SAT layer, so any testing help would be appreciated. These changes have been tested with Seagate Host Aware SATA drives attached to both SAS and SATA controllers. Also, I do not have any SATA Host Managed devices, and I suspect that it may take additional (hopefully minor) changes to support them. Thanks to Seagate for supplying the test hardware and answering questions. sbin/camcontrol/Makefile: Add epc.c and zone.c. sbin/camcontrol/camcontrol.8: Document the zone and epc subcommands. sbin/camcontrol/camcontrol.c: Add the zone and epc subcommands. Add auxiliary register support to build_ata_cmd(). Make sure to set the CAM_ATAIO_NEEDRESULT, CAM_ATAIO_DMA, and CAM_ATAIO_FPDMA flags as appropriate for ATA commands. Add a new get_ata_status() function to parse ATA result from SCSI sense descriptors (for ATA passthrough over SCSI) and ATA I/O requests. sbin/camcontrol/camcontrol.h: Update the build_ata_cmd() prototype Add get_ata_status(), zone(), and epc(). sbin/camcontrol/epc.c: Support for ATA Extended Power Conditions features. This includes support for all features documented in the ACS-4 Revision 12 specification from t13.org (dated February 18, 2016). The EPC feature set allows putting a drive into a power power mode immediately, or setting timeouts so that the drive will automatically enter progressively lower power states after various idle times. sbin/camcontrol/fwdownload.c: Update the firmware download code for the new build_ata_cmd() arguments. sbin/camcontrol/zone.c: Implement support for Shingled Magnetic Recording (SMR) drives via SCSI Zoned Block Commands (ZBC) and ATA Zoned Device ATA Command Set (ZAC). These specs were developed in concert, and are functionally identical. The primary differences are due to SCSI and ATA differences. (SCSI is big endian, ATA is little endian, for example.) This includes support for all commands defined in the ZBC and ZAC specs. sys/cam/ata/ata_all.c: Decode a number of additional ATA command names in ata_op_string(). Add a new CCB building function, ata_read_log(). Add ata_zac_mgmt_in() and ata_zac_mgmt_out() CCB building functions. These support both DMA and NCQ encapsulation. sys/cam/ata/ata_all.h: Add prototypes for ata_read_log(), ata_zac_mgmt_out(), and ata_zac_mgmt_in(). sys/cam/ata/ata_da.c: Revamp the ada(4) driver to support zoned devices. Add four new probe states to gather information needed for zone support. Add a new adasetflags() function to avoid duplication of large blocks of flag setting between the async handler and register functions. Add new sysctl variables that describe zone support and paramters. Add support for the new BIO_ZONE bio, and all of its subcommands: DISK_ZONE_OPEN, DISK_ZONE_CLOSE, DISK_ZONE_FINISH, DISK_ZONE_RWP, DISK_ZONE_REPORT_ZONES, and DISK_ZONE_GET_PARAMS. sys/cam/scsi/scsi_all.c: Add command descriptions for the ZBC IN/OUT commands. Add descriptions for ZBC Host Managed devices. Add a new function, scsi_ata_pass() to do ATA passthrough over SCSI. This will eventually replace scsi_ata_pass_16() -- it can create the 12, 16, and 32-byte variants of the ATA PASS-THROUGH command, and supports setting all of the registers defined as of SAT-4, Revision 5 (March 11, 2016). Change scsi_ata_identify() to use scsi_ata_pass() instead of scsi_ata_pass_16(). Add a new scsi_ata_read_log() function to facilitate reading ATA logs via SCSI. sys/cam/scsi/scsi_all.h: Add the new ATA PASS-THROUGH(32) command CDB. Add extended and variable CDB opcodes. Add Zoned Block Device Characteristics VPD page. Add ATA Return SCSI sense descriptor. Add prototypes for scsi_ata_read_log() and scsi_ata_pass(). sys/cam/scsi/scsi_da.c: Revamp the da(4) driver to support zoned devices. Add five new probe states, four of which are needed for ATA devices. Add five new sysctl variables that describe zone support and parameters. The da(4) driver supports SCSI ZBC devices, as well as ATA ZAC devices when they are attached via a SCSI to ATA Translation (SAT) layer. Since ZBC -> ZAC translation is a new feature in the T10 SAT-4 spec, most SATA drives will be supported via ATA commands sent via the SCSI ATA PASS-THROUGH command. The da(4) driver will prefer the ZBC interface, if it is available, for performance reasons, but will use the ATA PASS-THROUGH interface to the ZAC command set if the SAT layer doesn't support translation yet. As I mentioned above, ZBC command support is untested. Add support for the new BIO_ZONE bio, and all of its subcommands: DISK_ZONE_OPEN, DISK_ZONE_CLOSE, DISK_ZONE_FINISH, DISK_ZONE_RWP, DISK_ZONE_REPORT_ZONES, and DISK_ZONE_GET_PARAMS. Add scsi_zbc_in() and scsi_zbc_out() CCB building functions. Add scsi_ata_zac_mgmt_out() and scsi_ata_zac_mgmt_in() CCB/CDB building functions. Note that these have return values, unlike almost all other CCB building functions in CAM. The reason is that they can fail, depending upon the particular combination of input parameters. The primary failure case is if the user wants NCQ, but fails to specify additional CDB storage. NCQ requires using the 32-byte version of the SCSI ATA PASS-THROUGH command, and the current CAM CDB size is 16 bytes. sys/cam/scsi/scsi_da.h: Add ZBC IN and ZBC OUT CDBs and opcodes. Add SCSI Report Zones data structures. Add scsi_zbc_in(), scsi_zbc_out(), scsi_ata_zac_mgmt_out(), and scsi_ata_zac_mgmt_in() prototypes. sys/dev/ahci/ahci.c: Fix SEND / RECEIVE FPDMA QUEUED in the ahci(4) driver. ahci_setup_fis() previously set the top bits of the sector count register in the FIS to 0 for FPDMA commands. This is okay for read and write, because the PRIO field is in the only thing in those bits, and we don't implement that further up the stack. But, for SEND and RECEIVE FPDMA QUEUED, the subcommand is in that byte, so it needs to be transmitted to the drive. In ahci_setup_fis(), always set the the top 8 bits of the sector count register. We need it in both the standard and NCQ / FPDMA cases. sys/geom/eli/g_eli.c: Pass BIO_ZONE commands through the GELI class. sys/geom/geom.h: Add g_io_zonecmd() prototype. sys/geom/geom_dev.c: Add new DIOCZONECMD ioctl, which allows sending zone commands to disks. sys/geom/geom_disk.c: Add support for BIO_ZONE commands. sys/geom/geom_disk.h: Add a new flag, DISKFLAG_CANZONE, that indicates that a given GEOM disk client can handle BIO_ZONE commands. sys/geom/geom_io.c: Add a new function, g_io_zonecmd(), that handles execution of BIO_ZONE commands. Add permissions check for BIO_ZONE commands. Add command decoding for BIO_ZONE commands. sys/geom/geom_subr.c: Add DDB command decoding for BIO_ZONE commands. sys/kern/subr_devstat.c: Record statistics for REPORT ZONES commands. Note that the number of bytes transferred for REPORT ZONES won't quite match what is received from the harware. This is because we're necessarily counting bytes coming from the da(4) / ada(4) drivers, which are using the disk_zone.h interface to communicate up the stack. The structure sizes it uses are slightly different than the SCSI and ATA structure sizes. sys/sys/ata.h: Add many bit and structure definitions for ZAC, NCQ, and EPC command support. sys/sys/bio.h: Convert the bio_cmd field to a straight enumeration. This will yield more space for additional commands in the future. After change r297955 and other related changes, this is now possible. Converting to an enumeration will also prevent use as a bitmask in the future. sys/sys/disk.h: Define the DIOCZONECMD ioctl. sys/sys/disk_zone.h: Add a new API for managing zoned disks. This is very close to the SCSI ZBC and ATA ZAC standards, but uses integers in native byte order instead of big endian (SCSI) or little endian (ATA) byte arrays. This is intended to offer to the complete feature set of the ZBC and ZAC disk management without requiring the application developer to include SCSI or ATA headers. We also use one set of headers for ioctl consumers and kernel bio-level consumers. sys/sys/param.h: Bump __FreeBSD_version for sys/bio.h command changes, and inclusion of SMR support. usr.sbin/Makefile: Add the zonectl utility. usr.sbin/diskinfo/diskinfo.c Add disk zoning capability to the 'diskinfo -v' output. usr.sbin/zonectl/Makefile: Add zonectl makefile. usr.sbin/zonectl/zonectl.8 zonectl(8) man page. usr.sbin/zonectl/zonectl.c The zonectl(8) utility. This allows managing SCSI or ATA zoned disks via the disk_zone.h API. You can report zones, reset write pointers, get parameters, etc. Sponsored by: Spectra Logic Differential Revision: https://reviews.freebsd.org/D6147 Reviewed by: wblock (documentation)
* Add some device IDs from Intel Sunrise Point chipsets.mav2016-05-031-0/+9
| | | | MFC after: 2 weeks
* sys/dev: minor spelling fixes.pfg2016-05-032-3/+3
| | | | Most affect comments, very few have user-visible effects.
* Implement Auxiliary register. Add PIM_ATA_EXT flag to flag that a SIMimp2016-04-171-4/+7
| | | | | | | | | can handle it, and add the code to add it to the FIS that's sent to the drive. The mvs driver is the only other ATA driver in the system, and its hardware doesn't appear to support setting the Auxiliary register. Differential Revision: https://reviews.freebsd.org/D5598
* New CAM I/O scheduler for FreeBSD. The default I/O scheduler is the sameimp2016-04-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | as before. The common scheduling bits have moved from inline code in each of the CAM periph drivers into a library that implements the default scheduling. In addition, a number of rate-limiting and I/O preference options can be enabled by adding CAM_IOSCHED_NETFLIX to your config file. A number of extra stats are also maintained. CAM_IOSCHED_NETFLIX isn't on by default because it uses a separate BIO_READ and BIO_WRITE queue, so doesn't honor BIO_ORDERED between these two types of operations. We already didn't honor it for BIO_DELETE, and we don't depend on BIO_ORDERED between reads and writes anywhere in the system (it is currently used with BIO_FLUSH in ZFS to make sure some writes are complete before others start and as a poor-man's soft dependency in one place in UFS where we won't be issuing READs until after the operation completes). However, out of an abundance of caution, it isn't enabled by default. Plus, this also brings in NCQ TRIM support for those SSDs that support it. A black list is also provided for known rogues that use NCQ trim as an excuse to corrupt the drive. It was difficult to separate out into a separate commit. This code has run in production at Netflix for over a year now. Sponsored by: Netflix, Inc Differential Revision: https://reviews.freebsd.org/D4609
* Add hint.ahci.X.quirks tunable for some odd cases.mav2016-04-131-0/+2
| | | | MFC after: 2 weeks
* Cleanup unnecessary semicolons from the kernel.pfg2016-04-101-1/+1
| | | | Found with devel/coccinelle.
* Disable MSI-x for AHCI on Alpine plattformzbb2016-03-312-2/+7
| | | | | | | | | | | | Changes introduced to AHCI code adding support for MSI-x caused interrupt storm on Alpine boards. This is unintended behaviour so added quirk to omit this functionality. Reviewed by: mav Submitted by: Marcin Mazurek <mma@semihalf.com> Obtained from: Semihalf Sponsored by: Annapurna Labs Differential Revision: https://reviews.freebsd.org/D4301
* Convert a long to rman_res_t, fixing a sign extension bug.jhibbits2016-03-201-1/+1
| | | | | | | | | | | ahci.c had one signed long, which was passed into rman, rather than u_long. After the switch of rman_res_t from size u_long to size uintmax_t, the sign extension caused ranges to get messed up, and ahcich* to not attach. There may be more signed longs used in this way, which will be fixed as they're reported. Reported by: pho
* Convert rman to use rman_res_t instead of u_longjhibbits2016-01-272-2/+2
| | | | | | | | | | | | | | | | | | | | Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
* Add support for a generic AHCI attachment. This allows us to attach to aandrew2015-12-031-0/+131
| | | | | | | | | | | | | | | typically memory mapped bus, for example on the AMD Opteron A1100 the AHCI device is mapped in the CPUs address space, and not through a PCI controller. Further work is needed for this to work with ACPI as this is expected to be common on ARMv8 servers. Reviewed by: mav, mmel Obtained from: mmel, ABT Systems Ltd Relnotes: yes Sponsored by: SoftIron Inc Differential Revision: https://reviews.freebsd.org/D4269
* AHCI: Fix AHCI driver for ARM.mmel2015-11-292-0/+17
| | | | | | | | | | | On ARM, we must ensure proper interdevice write ordering. The AHCI interrupt status register must be updated in HW before registers in interrupt controller. Unfortunately, only way how we can do it is readback. Discussed with: mav Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D4240
* AHCI: Use bus_dmamap_sync(9) when accessing DMA buffers.mmel2015-11-281-3/+8
| | | | | | Reviewed by: mav Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D4240
* Allow AHCI driver attach to all known chips reporting RAID class.mav2015-09-221-1/+4
| | | | | Reported by: Michael BlackHeart <amdmiek@gmail.com> MFC after: 1 week
* Introduce support for MSI-X interrupts in AHCIzbb2015-07-223-19/+140
| | | | | | | | | | - Allocate resources for MSI-X table and PBA if necessary - Add function ahci_free_mem() to free all resources Reviewed by: jhb, mav Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3009
* Correct bit offsets for ahci quirkssmh2015-07-061-2/+2
| | | | | | | | Fix bit offsets causing incorrect quirks being reported on boot for ahci introduced by r280184. MFC after: 3 days Sponsored by: Multiplay
* Add AHCI attachment code for Allwinner A10/A20 SoCs.loos2015-07-032-0/+8
| | | | | | | | | | | | | | | | | | | | | The Allwinner SoC has an AHCI device on its internal main bus rather than the PCI bus. This SoC is somewhat underdocumented, and its SATA controller is no exception. The methods to support this chip were harvested from the Linux Allwinner SDK, and then constants invented to describe what's going on based on low-level constants contained in the SATA standard and guess work. This SoC requires a specific AHCI channel setup in order to start the operations on the channel properly. Clock setup and AHCI channel setup idea came from NetBSD. Tested on Cubieboard 2 and Banana pi (and attachment on Cubieboard by Pratik Singhal). Differential Revision: https://reviews.freebsd.org/D737 Submitted by: imp Reviewed by: imp, ganbold, mav, andrew
* Disable port multiplier support on Marvell 88SE61xx chips.mav2015-07-021-8/+8
| | | | | | | | | | According to report, some recent unrelated changes in the driver triggered timeouts when testing for absent port multiplier. Cause of this behavior channge is unclear, but since these chips are old, rare and buggy, it is easier to just disable port multiplier support, same as done in Linux. Reported by: bar MFC after: 3 days
* Restore AHCI quirks printing as base16.mav2015-06-021-1/+1
| | | | | | smh@ at r278034 made it base17, that is somewhat odd. :) MFC after: 3 days
* Reduce priority of ATA/SATA drivers.mav2015-03-233-6/+6
| | | | | | | Legacy ata(4) -> BUS_PROBE_LOW_PRIORITY; more functional ahci(4), siis(4), mvs(4) -> BUS_PROBE_DEFAULT; BUS_PROBE_VENDOR leave for vendor drivers. MFC after: 2 weeks
* Introduce Annapurna Labs AHCI supportzbb2015-03-173-1/+34
| | | | | | | | | | | | | | | Overview: * implemented quirk for forcing SATA interface enable * restore value to status register - this enables link autonegotiation Modifications: * devid:vendorid field * quirk for forcing PI setting (BIOS is doing that on PC-like systems) * write to capabilites field to enable phy link initialization Submitted by: Wojciech Macek <wma@semihalf.com> Reviewed by: imp, mav Obtained from: Semihalf
* Fix SATA Gen3 speed constants.mav2015-03-131-2/+2
| | | | MFC after: 1 week
* Update ThunderX SATA quirkemaste2015-03-041-1/+1
| | | | | | | | Add quirk to ThunderX AHCI forcing only 1 MSI-X interrupt. Shorten Thunder quirk description to avoid printing 'SATA' twice. Obtained from: Semihalf Sponsored by: The FreeBSD Foundation
* For some uniformity move ahci_ch_init() call under the lock.mav2015-02-261-1/+1
| | | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 2 weeks
* Add a quirk to limit AHCI MSI vectors to onesmh2015-02-012-27/+37
| | | | | | | | | | | | In 10.1-RELEASE the default number of MSI vectors used was changed from one to as many vectors as the HW supports. This change resulted in an ahci timeouts regression when running on AMD SB7x0/SB8x0/SB9x0 hardware, so its now limited to 1 MSI by default using this new quirk. MFC after: 2 weeks Sponsored by: Multiplay
* Complete r277100: add AHCI_Q_ABAR0 tp AHCI_Q_BIT_STRING.kib2015-01-131-1/+2
| | | | | Noted and reviewed by: smh MFC after: 6 days
* Add quirk to override default BAR(5) rid for AHCI.kib2015-01-132-2/+8
| | | | | | | | Use it for Cavium AHCI. Submitted by: Michaе┌ Stanek Reviewed by: imp (previous version) MFC after: 1 week
* - Const'ify the ahci_ids table.marius2014-12-283-9/+9
| | | | | | | - Use DEVMETHOD_END. - Use NULL instead of 0 for pointers. MFC after: 3 days
* style (9) nitssmh2014-12-211-7/+7
| | | | | | | | Use return (val); instead of return val; Differential Revision: D838 MFC after: 2 weeks Sponsored by: Multiplay
* Return the error from ahci_setup_interrupt in ahci_attachsmh2014-12-211-2/+2
| | | | | | | | | | | Previously ahci_attach returned a hard coded ENXIO instead of the value from ahci_setup_interrupt. This is effectively a NOOP change as currently ahci_setup_interrupt only ever returns 0 or ENXIO, so just there to protect against any future changes to that. Differential Revision: D838 MFC after: 2 weeks Sponsored by: Multiplay
* Clamp ahci max irq's to AHCI_MAX_IRQSsmh2014-12-211-0/+8
| | | | | | | | | | This prevents the possiblity of any overruns on the statically allocated struct irqs field. Differential Revision: D838 MFC after: 2 weeks X-MFC-With: r276012 Sponsored by: Multiplay
* Add a constant AHCI_MAX_IRQS removing magic numbersmh2014-12-211-1/+2
| | | | Sponsored by: Multiplay
* Add bunch of PCI IDs of Intel Wildcat Point (9 Series) chipsets.mav2014-11-261-0/+8
| | | | MFC after: 1 week
* Prevent overflow issues in timeout processingsmh2014-11-211-8/+8
| | | | | | | | | | | | | | | | | | | | | Previously, any timeout value for which (timeout * hz) will overflow the signed integer, will give weird results, since callout(9) routines will convert negative values of ticks to '1'. For unsigned integer overflow we will get sufficiently smaller timeout values than expected. Switch from callout_reset, which requires conversion to int based ticks to callout_reset_sbt to avoid this. Also correct isci to correctly resolve ccb timeout. This was based on the original work done by Eygene Ryabinkin <rea@freebsd.org> back in 5 Aug 2011 which used a macro to help avoid the overlow. Differential Revision: https://reviews.freebsd.org/D1157 Reviewed by: mav, davide MFC after: 1 month Sponsored by: Multiplay
* A dma tag alignment should be 1 (not 0) when a device can dma at any address.ian2014-11-061-1/+1
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* Use r271207 optimization only for MSI-enabled HBAs.mav2014-10-061-1/+1
| | | | | | | | | | It was found that VirtualBox' AHCI does not allow nterrupt to be cleared before the interrupt status register is read, causing interrupt storm. AHCI specification allows to skip this register use when multi-vector MSI is enabled and so interrupting port is known. For single-vector MSI that is not stated explicitly, but if the port is only one, it is obviously known too.
* Use a local STAILQ for unlocked done CCB processing in ahci direct modesmh2014-09-271-2/+8
| | | | | | | | | | | | | Previously it was possible for issues e.g. use after free, to result from processing the done queue while not holding the channel lock. While this should never happen in practice, unexpected code flows which result in two threads processing from the same queue may be possible. We now use a local STAILQ to prevent this ever being an issue. Sponsored by: Multiplay
* Initialize variables before resource_int_value().mav2014-09-121-0/+2
| | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>
* Add PCI ID for Promise TX8660 8-port 3Gbps HBA.mav2014-09-101-0/+1
| | | | | | | This device reports RAID subclass, but appears to be AHCI compatible. Submitted by: Yuri Perejilin <yuri@rivera.ru> MFC after: 1 week
* Bunch of microoptimizations to reduce dereferences and cache collisions.mav2014-09-083-163/+137
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* Save one register read (AHCI_IS) for AHCI controllers with only one port.mav2014-09-061-1/+3
| | | | | | | | For controllers with only one port (like PCIe or M.2 SSDs) interrupt can come from only one source, and skipping read saves few percents of CPU time. MFC after: 1 month H/W donated by: I/O Switch
* Restore order of interrupt setup. Minor problems can result byimp2014-09-062-7/+9
| | | | | | | setting up the interrupts too early: Reviewed by: mav@ Sponsored by: Netflix
* Fix typo in comments.mav2014-09-061-2/+3
| | | | | Submitted by: Benedict Reuschling <bcr@FreeBSD.org> MFC after: 6 days
* Invert AHCI_Q_NOBSYRES quirk meaning, waiting for readiness by default.mav2014-09-052-31/+36
| | | | | | | | | I gave up to update list of Marvell chips that require this quirk. The final nail was growing number of PCIe/M.2 SSDs where Marvell chips have PCI IDs of different vendors. MFC after: 1 week H/W donated by: I/O Switch
* Separate out PCI attachment from the main AHCI driver. Move checks ofimp2014-09-043-526/+646
| | | | | | | | | | | | | | PCI IDs into quirks, which mostly fit (though you'd get no argument from me that AHCI_Q_SATA1_UNIT0 is oddly specific). Set these quirks in the PCI attachment. Make some shared functions public so that PCI and possibly other bus attachments can use them. The split isn't perfect yet, but it is functional. The split will be perfected as other bus attachments for AHCI are written. Sponsored by: Netflix Reviewed by: kan, mav Differential Revision: https://reviews.freebsd.org/D699
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