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* Fix names of some Marvell SATA chips. It looks like chips with proprietarymav2012-03-021-4/+4
| | | | | | | | interface supported by mvs(4) are 88SX, while AHCI-like chips are 88SE. PR: kern/165271 Submitted by: Jia-Shiun Li <jiashiun@gmail.com> MFC after: 1 week
* Convert files to UTF-8uqs2012-01-151-1/+1
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* Add 0x2826 device ID for C600 (Patsburg) SATA controller in RAID mode.jimharris2012-01-061-0/+1
| | | | | Reviewed by: mav Approved by: scottl
* Add hw.ahci.force tunable to control whether AHCI drivers should attachmav2011-12-021-1/+5
| | | | | | | | | | to known AHCI-capable chips (AMD/NVIDIA), configured for legacy emulation. Enabled by default to get additional performance and functionality of AHCI when it can't be enabled by BIOS. Can be disabled to honor BIOS settings if needed for some reason. MFC after: 1 month
* Rename device_delete_all_children() into device_delete_children().hselasky2011-11-221-1/+1
| | | | | Suggested by: jhb @ and marius @ MFC after: 1 week
* Move the device_delete_all_children() function from usb_util.chselasky2011-11-191-7/+3
| | | | | | | | to kern/subr_bus.c. Simplify this function so that it no longer depends on malloc() to execute. Identify a few other places where it makes sense to use device_delete_all_children(). MFC after: 1 week
* Change the way how "not implemented" AHCI channels handled. Instead ofmav2011-11-171-5/+6
| | | | | | | | | | completely skipping them, create ahcich devices for them to allocate unit numbers, but mark them as disabled to prevent driver probe and attach. Last time some BIOSes tend to report unused channels as "not implemented". This change makes ahcichX devices numbering consistent, independently of connected disks. It makes per-channel driver hints usable and CAM devices wiring possible on such systems.
* Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.ed2011-11-071-1/+1
| | | | This means that their use is restricted to a single C file.
* Add one more ID for the Marvell 88SE9128 6Gbps SATA controller.mav2011-09-271-0/+1
| | | | MFC after: 3 days
* Add ID for ASMedia ASM1061 2-port PCIe 2.0 x1 6Gb/s SATA controller.mav2011-08-241-0/+1
| | | | | Approved by: re (blackend) MFC after: 1 week
* Do not force AHCI mode on NVIDIA MCP89 SATA controllers. Recent Applemav2011-08-021-1/+1
| | | | | | | | | Mac with this chipset does not initialize AHCI mode unless it is started from EFI loader. However, legacy ATA mode works. Submitted by: jkim@ (original version) Approved by: re (kib) MFC after: 1 week
* In some cases, at least on Marvell 88SE912x controllers, Current Commandmav2011-07-292-6/+15
| | | | | | | | | | | | Slot field of the PxCMD register may point to an empty command slot. That breaks command timeout detection logic, making impossible to find what command actually caused timeout, and leading to infinite wait. Workaround that by checking whether pointed command slot is really used and can timeout in its time. And if not, fallback to the dumb algorithm used with FBS -- let all commands to time out and then fail all of them. Approved by: re (kib) MFC after: 1 week
* Add ID for Marvell 88SE9125 SATA controller.mav2011-06-301-0/+1
| | | | | PR: kern/157843 MFC after: 1 week
* Add Marvell 88SE9172 chip PCI ID.mav2011-05-261-0/+1
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* Marvell 88SE91xx controllers are known to report soft-reset completionmav2011-05-261-28/+49
| | | | | | | | | | | | | | without waiting for device readiness (or at least not updating FIS receive area in time). To workaround that, special quirk was added earlier to wait for the FIS receive area update. But it was found that under same PCI ID 0x91231b4b and revision 0x11 there are two completely different chip versions (firmware?): HBA and RAID. The problem is that RAID version in some cases, such as hot-plug, does not update FIS receive area at all! To workaround that, differentiate the chip versions by their capabilities, and, if RAID version found, skip FIS receive area update waiting and read device signature from the PxSIG register instead. This method doesn't work for HBA version when PMP attached, so keep using previous workaround there.
* According to SATA specification, when Serial ATA Enclosure Management Bridgemav2011-05-251-12/+13
| | | | | | | | | | | | | | | | | | | | (SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in response to hard and soft resets it should among other things return value 0x7F in Status register. The weird side is that it means DRQ bit set, which tells that reset request is not completed. It would be fine if SEMB was the only device on port. But if SEMB connected to PMP or built into it, it may block access to other devices sharing same SATA port. Make some tunings/fixes to soft-reset handling to workaround the issue: - ahci(4): request CLO on the port after soft reset to ignore DRQ bit; - siis(4): gracefully reinitialize port after soft reset timeout (hardware doesn't detect reset request completion in this case); - mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it clear DRQ bit for us. For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726 PMPs, less important. Further, if hardware permit, I hope to implement real SEMB support.
* Add support for "LED" enclosure management messages, defined by the AHCI.mav2011-05-172-0/+83
| | | | | | | | | When supported by hardware, this allows to control per-port activity, locate and fault LEDs via the led(4) API for localization and status reporting purposes. Supporting AHCI controllers may transmit that information to the backplane controllers via SGPIO interface. Backplane controllers interpret received statuses in some way (IBPI standard) to report them using present indicators.
* Chipset support for the new Intel Panther Point PCH, thanksjfv2011-05-111-1/+9
| | | | to Seth Heasley for preparing the changes.
* Add PCI ID for Marvell 88SE9182 -- PCIe 2.x x2 relative of the 88SE912x.mav2011-05-051-0/+1
| | | | | Submitted by: dchagin MFC after: 1 week
* Fix some English grammar.mav2011-04-192-5/+5
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* According to specification. device should respond to COMRESET with COMINITmav2011-04-191-4/+9
| | | | | in no more then 10ms. If we detected no device presence within that time, there is no reason to wait longer.
* Properly handle memory allocation errors during error recovery.mav2011-04-191-5/+18
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* Handle ready timeout during polled operation same as done in mvs(4) before.mav2011-04-182-0/+6
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* - Tune different wait loops to cut some more milliseconds from reset time.mav2011-04-181-19/+19
| | | | | - Do not call ahci_start() before device signature received. It is required by the specification and caused non-fatal reset timeouts on AMD chipsets.
* Some changes around hot-plug and interface power-management:mav2011-04-152-15/+65
| | | | | | | | | | | | - use ATA_SE_EXCHANGED (SError.DIAG.X) bit to detect hot-plug events when power-management enabled and ATA_SE_PHY_CHANGED (SError.DIAG.N) can't be trusted; - on controllers supporting staggered spin-up (SS) put unused channels into Listen state instead of Off. It should still save some power, but allow plug-in events to be detected; - on controllers supporting cold presence detection (CPD), when power management enabled, use CPD events to detect hot-plug in addition to PHY events.
* Improve SATA Asynchronous Notification feature support in CAM:mav2011-04-131-1/+3
| | | | | | | | | | | | | - make SATA SIMs announce capabilities to handle SDB with Notification bit; - make PMP driver honor this SIMs capability; - make SATA XPT to negotiate and enable this feature for ATAPI devices. This feature allows supporting SATA ATAPI devices to inform system about some events happened, that may require attention. In my case this allows LG GH22LS50 SATA DVR-RW drive to report tray open/close events. Events reported to CAM in form of AC_SCSI_AEN async. Further they could be used as a hints for checking device status and reporting media change to upper layers, for example, via spoiling mechanism of GEOM.
* Refactor hard-reset implementation in ahci(4).mav2011-04-122-14/+74
| | | | | | | | | Instead of spinning in a tight loop for up to 15 seconds, polling for device readiness while it spins up, return reset completion just after PHY reports "connect well" or 100ms connection timeout. If device was found, use callout for checking device readiness with 100ms period up to full 31 second timeout. This fixes system freeze for 5-10 seconds on drives hot plug-in.
* Implement automatic SCSI sense fetching for ahci(4).mav2011-04-122-34/+93
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* Add one more ID for Marvell 88SE912x chip found on Asus U3S6 card.mav2011-04-071-0/+1
| | | | Submitted by: Jonas Jonsson <fatbrain@gmail.com>
* Add some more IDs of HighPoint RocketRAID 64x.mav2011-03-061-0/+2
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* Restore DH89xxCC/Patsburg chip IDs accentally dropped at r218596.mav2011-02-121-0/+4
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* Disable NCQ for multiport Marvell 88SX61XX SATA controllers. Simultaneousmav2011-02-121-10/+13
| | | | | | | | | active I/O to several disks (copying large file on ZFS) causes timeout after just a few seconds of run. Single port 88SX6111 seems like not affected. Skip reading transferred bytes count for these controllers. It works for 88SX6111, but 88SX6145 always returns zero there. Haven't tested others, but better to be safe.
* Support for the new Patsburg PCH chipset:jfv2011-02-011-1/+4
| | | | | | | | | | | - SMBus Controller - SATA Controller - HD Audio Controller - Watchdog Controller Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code. MFC after 3 days
* Support for the new DH89xxCC PCH chipset including:jfv2011-01-311-0/+1
| | | | | | - SATA controller - Watchdog timer - SMBus controller
* Add IDs for HighPoint RocketRAID 64x controllers.mav2011-01-101-0/+2
| | | | | | | | | | | | These controllers consist of two Marvell 88SE9128 6Gbps SATA chips and PLX PCIe bridge. As result, they seem to be agree to work with ahci(4) as usual HBAs. The only noticed issue is that RAID BIOS disables all drive caches during boot, though `camcontrol cmd ...` is able to fix that. Those who wants RAID functionality can still use closed proprietary driver from HighPoint site. MFC after: 1 week
* Add IDs of HighPoint RocketRAID 62x cards (Marvell 88SE9128 chips).mav2010-12-081-0/+4
| | | | | | PR: kern/152926 Submitted by: Mike Tancsa <mike@sentex.net> MFC after: 1 week
* Fix small typo.mav2010-11-221-1/+1
| | | | Submitted by: Artem Belevich
* Teach ahci(4), siis(4) and ATA_CAM ata(4) wrapper report to CAM residualmav2010-11-081-8/+22
| | | | I/O length on underruns, that often happens for some SCSI commands.
* Add missing mtx_destroy() on channel attach failure.mav2010-10-251-0/+1
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* Fix panic, when due to some kind of congestion on FIS-based switchingmav2010-09-161-5/+8
| | | | | | | port multiplier some command triggers false positive timeout, but then completes normally. MFC after: 2 weeks
* MFata(4):mav2010-08-281-8/+10
| | | | | Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.
* Export PCI IDs of ATA/SATA controllers through CAM and ata(4) layers tomav2010-07-251-2/+7
| | | | | GEOM. This information needed for proper soft-RAID's on-disk metadata reading and writing.
* Disable NCQ and PMP support for VIA VT8251 AHCI. It was reported to bemav2010-06-081-2/+2
| | | | unreliable under load. Linux does the same.
* Plug memory leak to silent Coverity. Error is still not really handled.mav2010-06-051-0/+1
| | | | | Found with: Coverity Prevent(tm) CID: 4130
* Fix attach errors handling.mav2010-06-051-3/+5
| | | | | Found with: Coverity Prevent(tm) CID: 3424
* Fill rman range start/end values. It makes devinfo output more readable.mav2010-05-221-0/+2
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* Report ATA/SATA channel number to NewBus at location string.mav2010-05-221-0/+12
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* Improve suspend/resume support. Make sure controller is idle on suspendmav2010-05-211-20/+49
| | | | and reset it on resume.
* Enable PCI busmastering explicitly to be sure.mav2010-05-021-0/+1
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* Make SATA XPT negotiate and enable some additional SATA features, such as:mav2010-05-022-70/+97
| | | | | | | - device initiated power management (some devices support only this way); - Automatic Partial to Slumber Transition (more power saving); - DMA auto-activation (expected to slightly improve performance). More features could be added later, when hardware supports.
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