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* Fix multicast handling. All Atheros controllers use big-endian formyongari2009-09-291-1/+1
| | | | | | in computing multicast hash. PR: kern/139137
* Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/rwatson2009-06-261-2/+2
| | | | | | | | | | | | | IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
* pci(4) handles PCIM_CMD_INTxDIS so there is no need to poke thisyongari2009-05-201-12/+0
| | | | bit in driver.
* o Don't access VPD even if hardware advertised the capability.yongari2009-03-282-134/+101
| | | | | | | | | | | | | | | | | | | | | | It seems that some revision of controller hang while accessing the VPD. Because VPD access routine are unused, nuke it. o Let TWSI reload EEPROM if VPD capability is detected. Reloading EEPROM will also set ethernet address so age(4) now reads AGE_PAR0 and AGE_PAR1 register to get ethernet address. This removes a lot of hack and enhance readability a lot. o Double PHY reset timeout as it takes more time to take PHY out of power-saving state. o Explicitly check power-saving state by checking undocumented PHY registers. If link is not up, poke undocumented registers to take PHY out of power-saving state. This is the same way what Linux does. On resume, make sure to wake up PHY. o Don't rely on auto-clearing feature of master reset bit, just wait 1ms and check idle status of MAC. o Add PCI device revision information in bootverbose mode. This should fix occasional controller hang in device attach phase. Reported by: barbara < barbara.xxx1975 at libero DOT it > Tested by: barbara < barbara.xxx1975 at libero DOT it >
* Fix inversed logic. pci_find_extcap() returns 0 when it findsyongari2009-03-231-1/+1
| | | | specified capability.
* Remove informational messages left. These messages were intended toyongari2008-11-071-7/+7
| | | | | | show up in verbose boot mode. Reported by: pluknet ( pluknet<> gmail DOT com )
* Remove unused age_txdqkevlo2008-10-211-2/+0
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* No need to sync descriptors twice in age_rxintr()kevlo2008-10-211-6/+0
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* Fix a typo: jme -> agekevlo2008-08-141-1/+1
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* Use DELAY() instead of pause if waiting time is less than 1ms.yongari2008-07-181-2/+2
| | | | | | This will fix driver hang if hz < 1000. Pointed out by: thompsa
* Fix typo in comment.rpaulo2008-06-081-1/+1
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* Add age(4), a driver for Attansic/Atheros L1 gigabit ethernetyongari2008-05-193-0/+4284
controller. L1 has several threshold/timer registers and they seem to require careful tuned parameters to get best performance. Datasheet for L1 is not available to open source driver writers so age(4) focus on stability and correctness of basic Tx/Rx operation. ATM the performance of age(4) is far from optimal which in turn means there are mis-programmed registers or incorrectly configured registers. Currently age(4) supports all known hardware assistance including - MSI support. - TCP Segmentation Offload. - Hardware VLAN tag insertion/stripping. - TCP/UDP checksum offload. - Interrupt moderation. - Hardware statistics counter support. - Jumbo frame support. - WOL support. L1 gigabit ethernet controller is mainly found on ASUS motherboards. Note, it seems that there are other variants of hardware as known as L2(Fast ethernet) and newer gigabit ethernet (AR81xx) from Atheros. These are not supported by age(4) and requires a seperate driver. Big thanks to all people who reported feedback or tested patches. Tested by: kevlo, bsam, Francois Ranchin < fyr AT fyrou DOT net > Thomas Nystroem < thn AT saeab DOT se > Roman Pogosyan < asternetadmin AT gmail DOT com > Derek Tattersal < dlt AT mebtel DOT net > Oliver Seitz < karlkiste AT yahoo DOT com >
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