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* Add two new options, FLASHADDR, which defines the address the flash iscognet2007-02-191-0/+2
| | | | | | | mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at at the time the kernel is booted. They are used to detect if the kernel is booted from the onboard flash. Define those for the IQ31244
* MFp4: add BWCT kernel configurationticso2007-01-051-0/+1
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* add CPU_XSCALE_IXP425sam2006-11-191-0/+1
| | | | | Reviewed by: cognet, imp MFC after: 1 month
* Finally bring it support for the i80219 XScale processor.cognet2006-08-241-0/+1
| | | | Submitted by: Max M. Boyarov <m.boyarov bsd by>
* Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it mapscognet2006-08-081-0/+1
| | | | | | | | whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
* For the moment, make board configuration a compile time option. Thisimp2006-07-141-0/+2
| | | | | saves space in the final kernel, but at the expense of flexibility to boot the same kernel accross a family of boards.
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-061-1/+0
| | | | completely nuke the !ARM32_NEW_VM_LAYOUT case.
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-0/+1
| | | | | | as an option. Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
* Resurrect Skyeye support :cognet2006-05-131-1/+2
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as acognet2006-04-061-0/+1
| | | | timecounter (because gxemul doesn't emule it yet).
* The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel optioncognet2005-12-091-0/+1
| | | | to override the frequency
* Add ARM_USE_SMALL_ALLOC.cognet2005-06-071-0/+1
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* Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit).cognet2005-02-261-0/+1
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* Add a new option, ARM32_NEW_VM_LAYOUT. When set, we try to put up to 4cognet2004-11-101-0/+2
| | | | | L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior. While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
* Add new options :cognet2004-09-231-5/+10
| | | | | | | | PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
* Add config magic for arm.cognet2004-05-141-0/+6
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