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* MFC r280278, r280402:ian2015-05-231-0/+1
| | | | | | Allow to override default kernel virtual address assignment on ARM. Do not save/restore the TLS pointer on context switch for armv6.
* MFC r274937:ian2014-12-271-0/+1
| | | | | | | Add ARMV6 as an arm option. This will cause obscure magic in config(8) to automatically set the armv6 option when MACHINE_ARCH is armv6. That allows replacing ever-growing lists of cpu names as options to compile a given file with the using either "optional armv6" or "optional !armv6".
* MFC r273703:ian2014-11-081-1/+0
| | | | Remove the ARM_DEVICE_MULTIPASS option and make its effect be the default.
* MFC r269594, r269596, r269597, r269598, r269605, r269606:ian2014-08-171-0/+1
| | | | | | | | | | | | | | | | | | | | | Set ofwbus and simplebus to attach during BUS_PASS_BUS. Define names that drivers can use to adjust their position relative to other drivers within a BUS_PASS Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that a platform can attach some other bus first if necessary. Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU. Attach arm generic interrupt and timer drivers in the middle of BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively. Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass device attachment on arm platforms. If this is defined, nexus attaches early in BUS_PASS_BUS, and other busses and devices attach later, in the pass number they are set up for. Without it defined, nexus attaches in BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
* MFC 264054, 264056ian2014-05-171-1/+0
| | | | | | | | Switch imx6 to using the mpcore per-cpu event timers, but continue to use the GPT timer, which is fixed-frequency, as a timecounter. Change NO_EVENTTIMERS from an arm-specific to an MI option, so that it can be used in MI code.
* MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,ian2014-05-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
* MFC r257549, r261642ian2014-05-151-1/+0
| | | | | | | | | Don't create a distinct free page pool for segregating allocations that are accessed through the direct map unless the kernel configuration actually includes a direct map. Only a few configurations do, and for the rest the unnecessary free page pool is a small pessimization. Remove the ARM_USE_SMALL_ALLOC option and code related to it.
* MFC r261252, r261279, r261304, r261305, r261322, r261336, r261337, r261338,ian2014-05-151-1/+0
| | | | | | | | | | | | | | | | | r261353 Fix the name of the dts file for the HL201... When mapping an address, the bsh needs the same offset we do for other things. Add explicit depends on bus_if.h and device_if.h to avoid a chicken and egg problem in some compilation environments. Switch to using PAs rather than VAs for the addresses we map for devices. This is a nop, except for what's reported by atmelbus for the resources. Comment cleanups. Move things around for diff reduction against FDT work.
* MFC r261038, r261039, r261040, r261041ian2014-05-141-0/+2
| | | | Implement generic support for early printf.
* MFC r260092, r260093, r260121, r260180,ian2014-05-141-0/+1
| | | | | | | | | | Allow AT91_MCI_ALLOW_OVERCLOCK to be an option in kernel config files. Set the SoC name for the atmelbus name. Add support for Samsung K9F2G08U0A (256MiB SLC) NAND Comment updates.
* MFC r258359, r258742, r258845, r259936, r259640ian2014-05-141-0/+1
| | | | | | | | | | | Apply access flags for managed and unmanaged pages properly on ARMv6/v7 Set the PGA_WRITEABLE flag when the protections indicate write access, not just when the current access is a write. Enable missing Access Flag for secondary cores on ARMv6/v7 Add identification and necessary type checks for Krait CPU cores.
* Rename device vfp to option VFP and retire the ARM_VFP_SUPPORT option. Thisandrew2013-08-171-0/+1
| | | | | | | simplifies enabling as previously both options were required to be enabled, now we only need a single option. While here enable VFP on the PandaBoard.
* Remove the ARMFPE option. It is unsupported, and appears to be broken asandrew2013-08-171-1/+0
| | | | arm_fpe_core_changecontext is not a function.
* Port the new PV entry allocator from amd64/i386/mips to armv6/v7.gber2013-05-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PV entries are now roughly half the size. Instead of using a shared UMA zone for 28 byte pv entries (two 8-byte tailq nodes, a 4 byte pointer, a 4 byte address and 4 byte flags), we allocate a page at a time per process. This provides 252 pv entries per process (actually, per pmap address space) and eliminates one of the 8-byte tailq entries since we now can track per-process pv entries implicitly. The pointer to the pmap can be eliminated by doing address arithmetic to find the metadata on the page headers to find a single pointer shared by all 252 entries. There is an 8-int bitmap for the freelist of those 252 entries. When in serious low memory condition, allocation of another pv_chunk is possible by freeing some pages in pmap_pv_reclaim(). Added pv_entry/pv_chunk related statistics to pmap. pv_entry/pv_chunk statistics can be accessed via sysctl vm.pmap. Ported PTE freelist of KVA allocation and maintenance from i386. Using an idea from Stephan Uphoff, use the empty pte's that correspond to the unused kva in the pv memory block to thread a freelist through. This allows us to free pages that used to be used for pv entry chunks since we can now track holes in the kva memory block. As both ARM pmap.c and pmap-v6.c use the same header and pv_entry, pmap and md_page structures are different, it was needed to separate code designed for ARMv6/7 from the one for other ARMs. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Reviewed by: alc Sponsored by: The FreeBSD Foundation, Semihalf
* Replace generic ARM11 option with more specificgonzo2012-12-201-1/+2
| | | | | | | support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
* Piggyback MIPS changes and add ARM syscons support for devices withgonzo2012-08-251-0/+3
| | | | | | framebuffer While here - sort #if defined() order alphabetically
* Merging projects/armv6, part 1gonzo2012-08-151-4/+22
| | | | | | | | | Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
* Create a generic way to support multiple boards within animp2012-07-071-0/+1
| | | | | | arm platform. Add all the atmel boards to the ATMEL kernel for testing purposes. Until boot loader arg parsing of baord type is done, this won't actually be able to do the runtime selection.
* These options are unused, and can safely be retired.imp2012-06-151-4/+0
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* Add support for parsing Linux ATAGs such as you'd see from uboot orimp2012-06-141-0/+1
| | | | | | | redboot. Support is very preiminary and likely needs some work. Also, do some minor code shuffling of the FreeBSD /boot/loader metadata parsing code. This code is preliminary and should be used with caution.
* Create default_parse_boot_param which, if FreeBSD /boot/loader supportimp2012-06-141-0/+1
| | | | | | | | | is enabled, sets values based on the metadata passed in. Otherwise fake_preload_metadata is called. Change the default parse_boot_param to default_parse_boot_param. Enable this functionality only on the mv platform, which is where most of the code is from. Reviewed by: cognet, Ian Lapore
* Eliminate the now-unused AT91C_MASTER_CLOCK option and change the oneimp2012-06-041-2/+1
| | | | | place in the source it was used to the more correct AT91C_MAIN_CLOCK. Sort AT91C_MAIN_CLOCK into a better location in the options.arm file.
* - Add new ARM kernel option QEMU_WORKAROUNDS which can bestas2012-04-071-0/+1
| | | | | | | used in the code which needs to implement some specific behaviour when being run under QEMU. - Make PXA UART probe code to work under QEMU gumstix, which doesn't emulate all the ports properly.
* Add options I missed in the additionnal AT91 support commits.cognet2010-10-071-0/+3
| | | | Submitted by: Greg Ansley
* Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option.raj2010-07-191-1/+0
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* Convert Marvell ARM platforms to FDT convention.raj2010-06-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are involved: - DB-88F5182 - DB-88F5281 - DB-88F6281 - DB-78100 - SheevaPlug This overhaul covers the following major changes: - All integrated peripherals drivers for Marvell ARM SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say good by to obio / mbus drivers and numerous hard-coded config data. Note that world needs to be built WITH_FDT for the affected platforms. Reviewed by: imp Sponsored by: The FreeBSD Foundation.
* Add support for FA626TE.kevlo2010-05-041-0/+1
| | | | Tested on GM8181 development board.
* Add support for Cavium Econa CNS11XX ARM boards. These boards wererpaulo2010-01-041-0/+1
| | | | | | | | | | previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
* Introduce MII_ADDR_BASE option on ARM, which allows to override the defaultraj2009-08-251-0/+1
| | | | | | | | | | | | | | per platform requirements. Notes: - Only used by mge(4) at the moment. - This is very simplified approach and should be replaced by some long-term solution for managing the board/platform configuration (among others the MAC-PHY binding info). Submitted by: Michal Hajduk Obtained from: Semihalf
* add IXP4XX_FLASH_SIZE config knob that can be used to override the defaultsam2009-03-101-0/+1
| | | | | flash size; this is necessary at the moment because we map all of flash at boot, eventually we'll do this on the fly
* Merge WIP from p4:sam2008-12-131-0/+1
| | | | | | | | | | | | | | | | | | o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
* - Obtain main clock frequency dynamically based on CKGR_MCFR registerstas2008-11-301-0/+1
| | | | | | | | | | | contents. - It is possible to override the dynamic configuration by using AT91C_MAIN_CLOCK option in kernel config. PR: arm/128961 (based on) Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de> Reviewed by: imp Approved by: kib (mentor, implicit)
* Introduce basic support for Marvell families of system-on-chip ARM devices:raj2008-10-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
* Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connexbenno2008-06-061-0/+1
| | | | | | | | | | | | | boards. This is enough to net-boot to multiuser. Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC add-on boards. I'll be putting some instructions on how to boot this on the Gumstix boards online soon. This is still fairly rough and will be refined over time but I felt it was better to get this out there where other people can help out.
* Add CPU_ARM9Ekevlo2007-10-311-0/+1
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* Add an option to be able to override the value of the AT91 master clockcognet2007-10-251-0/+1
| | | | | frequency. It'd be better to be able to calculate it at runtime, but we need the information very early, to setup the uart.
* Add CPU_XSCALE_81342 before I forget again.cognet2007-06-111-1/+2
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* Add two new options, FLASHADDR, which defines the address the flash iscognet2007-02-191-0/+2
| | | | | | | mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at at the time the kernel is booted. They are used to detect if the kernel is booted from the onboard flash. Define those for the IQ31244
* MFp4: add BWCT kernel configurationticso2007-01-051-0/+1
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* add CPU_XSCALE_IXP425sam2006-11-191-0/+1
| | | | | Reviewed by: cognet, imp MFC after: 1 month
* Finally bring it support for the i80219 XScale processor.cognet2006-08-241-0/+1
| | | | Submitted by: Max M. Boyarov <m.boyarov bsd by>
* Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it mapscognet2006-08-081-0/+1
| | | | | | | | whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
* For the moment, make board configuration a compile time option. Thisimp2006-07-141-0/+2
| | | | | saves space in the final kernel, but at the expense of flexibility to boot the same kernel accross a family of boards.
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-061-1/+0
| | | | completely nuke the !ARM32_NEW_VM_LAYOUT case.
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-0/+1
| | | | | | as an option. Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
* Resurrect Skyeye support :cognet2006-05-131-1/+2
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as acognet2006-04-061-0/+1
| | | | timecounter (because gxemul doesn't emule it yet).
* The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel optioncognet2005-12-091-0/+1
| | | | to override the frequency
* Add ARM_USE_SMALL_ALLOC.cognet2005-06-071-0/+1
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* Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit).cognet2005-02-261-0/+1
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