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* Add options I missed in the additionnal AT91 support commits.cognet2010-10-071-0/+3
| | | | Submitted by: Greg Ansley
* Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option.raj2010-07-191-1/+0
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* Convert Marvell ARM platforms to FDT convention.raj2010-06-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are involved: - DB-88F5182 - DB-88F5281 - DB-88F6281 - DB-78100 - SheevaPlug This overhaul covers the following major changes: - All integrated peripherals drivers for Marvell ARM SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say good by to obio / mbus drivers and numerous hard-coded config data. Note that world needs to be built WITH_FDT for the affected platforms. Reviewed by: imp Sponsored by: The FreeBSD Foundation.
* Add support for FA626TE.kevlo2010-05-041-0/+1
| | | | Tested on GM8181 development board.
* Add support for Cavium Econa CNS11XX ARM boards. These boards wererpaulo2010-01-041-0/+1
| | | | | | | | | | previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
* Introduce MII_ADDR_BASE option on ARM, which allows to override the defaultraj2009-08-251-0/+1
| | | | | | | | | | | | | | per platform requirements. Notes: - Only used by mge(4) at the moment. - This is very simplified approach and should be replaced by some long-term solution for managing the board/platform configuration (among others the MAC-PHY binding info). Submitted by: Michal Hajduk Obtained from: Semihalf
* add IXP4XX_FLASH_SIZE config knob that can be used to override the defaultsam2009-03-101-0/+1
| | | | | flash size; this is necessary at the moment because we map all of flash at boot, eventually we'll do this on the fly
* Merge WIP from p4:sam2008-12-131-0/+1
| | | | | | | | | | | | | | | | | | o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
* - Obtain main clock frequency dynamically based on CKGR_MCFR registerstas2008-11-301-0/+1
| | | | | | | | | | | contents. - It is possible to override the dynamic configuration by using AT91C_MAIN_CLOCK option in kernel config. PR: arm/128961 (based on) Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de> Reviewed by: imp Approved by: kib (mentor, implicit)
* Introduce basic support for Marvell families of system-on-chip ARM devices:raj2008-10-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
* Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connexbenno2008-06-061-0/+1
| | | | | | | | | | | | | boards. This is enough to net-boot to multiuser. Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC add-on boards. I'll be putting some instructions on how to boot this on the Gumstix boards online soon. This is still fairly rough and will be refined over time but I felt it was better to get this out there where other people can help out.
* Add CPU_ARM9Ekevlo2007-10-311-0/+1
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* Add an option to be able to override the value of the AT91 master clockcognet2007-10-251-0/+1
| | | | | frequency. It'd be better to be able to calculate it at runtime, but we need the information very early, to setup the uart.
* Add CPU_XSCALE_81342 before I forget again.cognet2007-06-111-1/+2
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* Add two new options, FLASHADDR, which defines the address the flash iscognet2007-02-191-0/+2
| | | | | | | mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at at the time the kernel is booted. They are used to detect if the kernel is booted from the onboard flash. Define those for the IQ31244
* MFp4: add BWCT kernel configurationticso2007-01-051-0/+1
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* add CPU_XSCALE_IXP425sam2006-11-191-0/+1
| | | | | Reviewed by: cognet, imp MFC after: 1 month
* Finally bring it support for the i80219 XScale processor.cognet2006-08-241-0/+1
| | | | Submitted by: Max M. Boyarov <m.boyarov bsd by>
* Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it mapscognet2006-08-081-0/+1
| | | | | | | | whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
* For the moment, make board configuration a compile time option. Thisimp2006-07-141-0/+2
| | | | | saves space in the final kernel, but at the expense of flexibility to boot the same kernel accross a family of boards.
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-061-1/+0
| | | | completely nuke the !ARM32_NEW_VM_LAYOUT case.
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-0/+1
| | | | | | as an option. Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
* Resurrect Skyeye support :cognet2006-05-131-1/+2
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as acognet2006-04-061-0/+1
| | | | timecounter (because gxemul doesn't emule it yet).
* The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel optioncognet2005-12-091-0/+1
| | | | to override the frequency
* Add ARM_USE_SMALL_ALLOC.cognet2005-06-071-0/+1
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* Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit).cognet2005-02-261-0/+1
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* Add a new option, ARM32_NEW_VM_LAYOUT. When set, we try to put up to 4cognet2004-11-101-0/+2
| | | | | L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior. While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
* Add new options :cognet2004-09-231-5/+10
| | | | | | | | PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
* Add config magic for arm.cognet2004-05-141-0/+6
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