| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
Submitted by: Greg Ansley
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The following systems are involved:
- DB-88F5182
- DB-88F5281
- DB-88F6281
- DB-78100
- SheevaPlug
This overhaul covers the following major changes:
- All integrated peripherals drivers for Marvell ARM SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).
- Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
good by to obio / mbus drivers and numerous hard-coded config data.
Note that world needs to be built WITH_FDT for the affected platforms.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation.
|
|
|
|
| |
Tested on GM8181 development board.
|
|
|
|
|
|
|
|
|
|
| |
previously know by StarSemi STR9104.
Tested by the submitter on an Emprex NSD-100 board.
Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
per platform requirements.
Notes:
- Only used by mge(4) at the moment.
- This is very simplified approach and should be replaced by some long-term
solution for managing the board/platform configuration (among others the
MAC-PHY binding info).
Submitted by: Michal Hajduk
Obtained from: Semihalf
|
|
|
|
|
| |
flash size; this is necessary at the moment because we map all of flash at
boot, eventually we'll do this on the fly
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
|
|
|
|
|
|
|
|
|
|
|
| |
contents.
- It is possible to override the dynamic configuration by using
AT91C_MAIN_CLOCK option in kernel config.
PR: arm/128961 (based on)
Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de>
Reviewed by: imp
Approved by: kib (mentor, implicit)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
boards. This is enough to net-boot to multiuser.
Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC
add-on boards.
I'll be putting some instructions on how to boot this on the Gumstix boards
online soon.
This is still fairly rough and will be refined over time but I felt it was
better to get this out there where other people can help out.
|
| |
|
|
|
|
|
| |
frequency. It'd be better to be able to calculate it at runtime, but we need
the information very early, to setup the uart.
|
| |
|
|
|
|
|
|
|
| |
mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at
at the time the kernel is booted.
They are used to detect if the kernel is booted from the onboard flash.
Define those for the IQ31244
|
| |
|
|
|
|
|
| |
Reviewed by: cognet, imp
MFC after: 1 month
|
|
|
|
| |
Submitted by: Max M. Boyarov <m.boyarov bsd by>
|
|
|
|
|
|
|
|
| |
whole the physical memory, cached, using 1MB section mappings. This reduces
the address space available for user processes a bit, but given the amount of
memory a typical arm machine has, it is not (yet) a big issue.
It then provides a uma_small_alloc() that works as it does for architectures
which have a direct mapping.
|
|
|
|
|
| |
saves space in the final kernel, but at the expense of flexibility to
boot the same kernel accross a family of boards.
|
|
|
|
| |
completely nuke the !ARM32_NEW_VM_LAYOUT case.
|
|
|
|
|
|
| |
as an option.
Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds
workarounds for things skyeye doesn't simulate. Specifically :
- Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function.
- Skyeye maintains an internal counter for clock, but apparently there's
no way to access it, so hack the timecounter code to return a value which
is increased at every clock interrupts. This is gross, but I didn't find a
better way to implement timecounters without hacking Skyeye to get the
counter value.
- Force the write-back of PTEs once we're done writing them, even if they
are supposed to be write-through. I don't know why I have to do that.
|
|
|
|
| |
timecounter (because gxemul doesn't emule it yet).
|
|
|
|
| |
to override the frequency
|
| |
|
| |
|
|
|
|
|
| |
L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior.
While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
|
|
|
|
|
|
|
|
| |
PHYSADDR : Address of the physical memory
KERNPHYSADDR : Physical address where the kernel starts
KERNVIRTADDR : Virtual address of the kernel
STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap
+ Xscale specific options
|
|
|