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* Show the cpu info for fa526kevlo2010-02-203-1/+7
| | | | Submitted by: Yohanes Nugroho <yohanes at gmail dot com>
* Correct both FA526/FA626TE cpu ids since the cpu id is alwayskevlo2010-02-201-2/+2
| | | | masked with 0xfffffff0
* The NetBSD Foundation has granted permission to remove clauses 3 and 4.imp2010-02-1616-112/+0
| | | | Obtained from: NetBSD
* Adjust style (following the already existing rules) for the newlyattilio2010-02-1514-14/+14
| | | | | | introduced option DEADLKRES. Reported by: danfe, julian, avg
* Correct cpu id for FA526.kevlo2010-02-141-1/+2
| | | | While I'm here, add cpu id for FA626TE.
* Add the options DEADLKRES (introducing the deadlock resolver thread) inattilio2010-02-1016-0/+16
| | | | | | | | | | the 'debugging' section of any HEAD kernel and enable for the mainstream ones, excluding the embedded architectures. It may, of course, enabled on a case-by-case basis. Sponsored by: Sandvine Incorporated Requested by: emaste Discussed with: kib
* Turn on the front LED at boot time like we do with the Avila.rpaulo2010-02-101-0/+2
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* Improve checking whether an ARM VA has a valid mapping before performing cacheraj2010-02-071-74/+42
| | | | | | | | | | | | | | | | | | | | sync. VIPT/PIPT caches need valid VA-PA mapping in PTE for a cache operation to succeed (unlike VIVT). Prior to this fix pmap was using l2pte_valid() for that check, but this is not sufficient as the function merely checks if a PTE exists (there can be existing but _invalid_ entries in the table). A new pmap_has_valid_mapping() routine is introduced to do this job right by checking proper PTE flags. Among other potential problems this cures coherency issues with L2 caches on MV-78100. Submitted by: Grzegorz Bernacki, Piotr Ziecik Reviewed, tested by: marcel Obtained from: Semihalf MFC after: 1 week
* When backtracing self, start with the current frame (i.e. themarcel2010-01-291-1/+1
| | | | | | frame of db_trace_self()) and not the caller's frame. The use of builtin_frame_address(1) to get the caller's frame is not reliable and can cause panics.
* Move the examples for the 'hints' and 'env' keywords from various GENERICjhb2010-01-196-12/+0
| | | | | | kernel configs into NOTES. Reviewed by: imp
* Do not free the dmamap if it is still busy.cognet2010-01-151-1/+1
| | | | | Submitted by: Mark Tinguely MFC after: 3 days
* Revert 200594. This file isn't intended for these sorts of things.imp2010-01-041-7/+0
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* Remove CNS11XXNAS.hints.rpaulo2010-01-042-3/+0
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* Add support for Cavium Econa CNS11XX ARM boards. These boards wererpaulo2010-01-0422-3/+5368
| | | | | | | | | | previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
* Update d_mmap() to accept vm_ooffset_t and vm_memattr_t.rnoland2009-12-291-2/+2
| | | | | | | | | | | | | This replaces d_mmap() with the d_mmap2() implementation and also changes the type of offset to vm_ooffset_t. Purge d_mmap2(). All driver modules will need to be rebuilt since D_VERSION is also bumped. Reviewed by: jhb@ MFC after: Not in this lifetime...
* Intel XScale hwpmc(4) support.rpaulo2009-12-234-6/+51
| | | | | | | | | | | This brings hwpmc(4) support for 2nd and 3rd generation XScale cores. Right now it's enabled by default to make sure we test this a bit. When the time comes it can be disabled by default. Tested on Gateworks boards. A man page is coming. Obtained from: //depot/user/rpaulo/xscalepmc/...
* Add INCLUDE_CONFIG_FILE, and a note in comments about how to alsodougb2009-12-161-0/+7
| | | | include the comments with CONFIGARGS
* Fix the build.mav2009-12-081-2/+13
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* MFp4:mav2009-12-061-10/+4
| | | | | | | | | | | | | | | | | | Introduce ATA_CAM kernel option, turning ata(4) controller drivers into cam(4) interface modules. When enabled, this options deprecates all ata(4) peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers (ada, cd, ...) and interfaces to be natively used instead. As side effect of this, ata(4) mode setting code was completely rewritten to make controller API more strict and permit above change. While doing this, SATA revision was separated from PATA mode. It allows DMA-incapable SATA devices to operate and makes hw.ata.atapi_dma tunable work again. Also allow ata(4) controller drivers (except some specific or broken ones) to handle larger data transfers. Previous constraint of 64K was artificial and is not really required by PCI ATA BM specification or hardware. Submitted by: nwitehorn (powerpc part)
* Add missing ath_ar9* ath hal entries.thompsa2009-12-021-0/+1
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* Remove unknown ath hal device entries.thompsa2009-12-021-3/+0
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* Simplify the invocation of vm_fault(). Specifically, eliminate the flagalc2009-11-271-2/+1
| | | | | | | VM_FAULT_DIRTY. The information provided by this flag can be trivially inferred by vm_fault(). Discussed with: kib
* - Initialize callout before it is used in atestop() during attach.jhb2009-11-191-9/+5
| | | | | | | | - Reorder detach so that ether_ifdetach() is called first. This removes the race that ATE_FLAG_DETACHING closed, so that flag can be removed. - Trim a duplicate clearing of IFF_DRV_RUNNING. Reviewed by: imp
* These drivers only set if_timer but never set if_watchdog. Just removejhb2009-11-191-2/+0
| | | | the assignments to if_timer.
* Extract the code that records syscall results in the frame into MDkib2009-11-102-36/+54
| | | | | | | | | | | function cpu_set_syscall_retval(). Suggested by: marcel Reviewed by: marcel, davidxu PowerPC, ARM, ia64 changes: marcel Sparc64 tested and reviewed by: marius, also sunv reviewed MIPS tested by: gonzo MFC after: 1 month
* Fix gdb_cpu_getreg() to actually match GDB's registermarcel2009-11-051-3/+7
| | | | definition.
* Implement db_trace_thread() by calling db_stack_trace_cmd() andmarcel2009-11-051-6/+3
| | | | | passing a frame pointer that comes from the thread context. This fixes DDB backtraces by not unwinding debugger functions first.
* Implement db_trace_self() by calling db_stack_trace_cmd()marcel2009-11-051-1/+4
| | | | and not db_trace_thread().
* Eliminate an unnecessary vm include file.alc2009-11-044-4/+0
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* MFp4:mav2009-10-311-7/+6
| | | | | | | | - Remove most of direct relations between ATA(4) peripherial and controller levels. It makes logic more transparent and is a mandatory step to wrap ATA(4) controller level into ATA-native CAM SIM. - Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger I/O transaction sizes without additional cost.
* In r197963, a race with thread being selected for signal deliverykib2009-10-271-6/+1
| | | | | | | | | | | | | while in kernel mode, and later changing signal mask to block the signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls. Use kern_sigprocmask() instead of direct manipulation of td_sigmask to reschedule newly blocked signals, closing the race. Reviewed by: davidxu Tested by: pho MFC after: 1 month
* Review previous change. It has no relation to the I-cache coherencymarcel2009-10-211-1/+1
| | | | | | changes and thus unintentional. Spotted by: rdivacky@
* o Introduce vm_sync_icache() for making the I-cache coherent withmarcel2009-10-212-3/+9
| | | | | | | | | | | | | | | | | | | | | the memory or D-cache, depending on the semantics of the platform. vm_sync_icache() is basically a wrapper around pmap_sync_icache(), that translates the vm_map_t argumument to pmap_t. o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc it replaces the pmap_page_executable() function, added to solve the I-cache problem in uiomove_fromphys(). o In proc_rwmem() call vm_sync_icache() when writing to a page that has execute permissions. This assures that when breakpoints are written, the I-cache will be coherent and the process will actually hit the breakpoint. o This also fixes the Book-E PMAP implementation that was missing necessary locking while trying to deal with the I-cache coherency in pmap_enter() (read: mmu_booke_enter_locked). The key property of this change is that the I-cache is made coherent *after* writes have been done. Doing it in the PMAP layer when adding or changing a mapping means that the I-cache is made coherent *before* any writes happen. The difference is key when the I-cache prefetches.
* Sync with other GENERIC kernel configs:jhb2009-10-132-23/+31
| | | | | | | | - Move USB serial drivers earlier to match their placement in other kernel configs. - Add descriptions to various USB drivers. - Move the USB wireless drivers into a new section. - Add ulscom to the list of USB serial drivers.
* Define architectural load bases for PIE binaries. Addresses were selectedkib2009-10-101-0/+3
| | | | | | | | | | by looking at the bases used for non-relocatable executables by gnu ld(1), and adjusting it slightly. Discussed with: bz Reviewed by: kan Tested by: bz (i386, amd64), bsam (linux) MFC after: some time
* - Drop unused pmap_use_l1 function and comment out currently unusedstas2009-10-051-46/+8
| | | | | | | | pmap_dcache_wbinv_all/pmap_copy_page functions which we might want to take advatage of later. This fixes the build with PMAP_DEBUG defined. Discussed with: cognet
* Remove remaining bits of performance counter support.rpaulo2009-10-032-26/+0
| | | | Submitted by: Tom Judge <tom at tomjudge.com>
* Make sure that the primary native brandinfo always gets addedbz2009-10-031-1/+1
| | | | | | | | | | | | | first and the native ia32 compat as middle (before other things). o(ld)brandinfo as well as third party like linux, kfreebsd, etc. stays on SI_ORDER_ANY coming last. The reason for this is only to make sure that even in case we would overflow the MAX_BRANDS sized array, the native FreeBSD brandinfo would still be there and the system would be operational. Reviewed by: kib MFC after: 1 month
* Remove performance counter headers. This code came from NetBSD, but ourrpaulo2009-10-023-150/+0
| | | | | | | hardware perf. counter support is different, so we don't need these files. Reviewed by: freebsd-arm (no comments)
* Promote the cpu_class local variable to global and expose it in md_var.hrpaulo2009-09-262-20/+23
| | | | Reviewed by: freebsd-arm
* Add a new sysctl for reporting all of the supported page sizes.alc2009-09-181-0/+2
| | | | | Reviewed by: jhb MFC after: 3 weeks
* Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating anphk2009-09-082-18/+57
| | | | | architecture specific include file containing the _ALIGN* stuff which <sys/socket.h> needs.
* Reintroduce the r196640, after fixing the problem with my testing.kib2009-09-011-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Remove the altkstacks, instead instantiate threads with kernel stack allocated with the right size from the start. For the thread that has kernel stack cached, verify that requested stack size is equial to the actual, and reallocate the stack if sizes differ [1]. This fixes the bug introduced by r173361 that was committed several days after r173004 and consisted of kthread_add(9) ignoring the non-default kernel stack size. Also, r173361 removed the caching of the kernel stacks for a non-first thread in the process. Introduce separate kernel stack cache that keeps some limited amount of preallocated kernel stacks to lower the latency of thread allocation. Add vm_lowmem handler to prune the cache on low memory condition. This way, system with reasonable amount of the threads get lower latency of thread creation, while still not exhausting significant portion of KVA for unused kstacks. Submitted by: peter [1] Discussed with: jhb, julian, peter Reviewed by: jhb Tested by: pho (and retested according to new test scenarious) MFC after: 1 week
* Reverse r196640 and r196644 for now.kib2009-08-291-0/+3
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* Remove the altkstacks, instead instantiate threads with kernel stackkib2009-08-291-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | allocated with the right size from the start. For the thread that has kernel stack cached, verify that requested stack size is equial to the actual, and reallocate the stack if sizes differ [1]. This fixes the bug introduced by r173361 that was committed several days after r173004 and consisted of kthread_add(9) ignoring the non-default kernel stack size. Also, r173361 removed the caching of the kernel stacks for a non-first thread in the process. Introduce separate kernel stack cache that keeps some limited amount of preallocated kernel stacks to lower the latency of thread allocation. Add vm_lowmem handler to prune the cache on low memory condition. This way, system with reasonable amount of the threads get lower latency of thread creation, while still not exhausting significant portion of KVA for unused kstacks. Submitted by: peter [1] Discussed with: jhb, julian, peter Reviewed by: jhb Tested by: pho MFC after: 1 week
* revert r196600; didn't notice it'd been done alreadysam2009-08-271-1/+0
| | | | Submitted by: jhay
* enable mesh by defaultsam2009-08-271-0/+1
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* Introduce SheevaPlug support.raj2009-08-254-0/+234
| | | | | | | | | | | | | - The device is based on Marvell 88F6281 system on chip. - More info about the platform at http://www.plugcomputer.org - To build the FreeBSD kernel: make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG - Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell Submitted by: Michal Hajduk Obtained from: Semihalf
* Exclude common Kirkwood settings so they can be shared among various platformsraj2009-08-254-8/+21
| | | | | | | based on this SOC. This is a preliminary step for SheevaPlug support. Submitted by: Michal Hajduk Obtained from: Semihalf
* Properly handle initial state of power mgmt.raj2009-08-253-2/+134
| | | | | | | | | | Modules on Marvell SOC can be selectively PM-disabled, and we must not access disabled devices' registers (attempt to initialize them) unconditionally, as this leads to the system hang. This patch introduces graceful handling of the PM state during devices init. Submitted by: Michal Hajduk Obtained from: Semihalf
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