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* o Introduce vm_sync_icache() for making the I-cache coherent withmarcel2009-10-212-3/+9
* Sync with other GENERIC kernel configs:jhb2009-10-132-23/+31
* Define architectural load bases for PIE binaries. Addresses were selectedkib2009-10-101-0/+3
* - Drop unused pmap_use_l1 function and comment out currently unusedstas2009-10-051-46/+8
* Remove remaining bits of performance counter support.rpaulo2009-10-032-26/+0
* Make sure that the primary native brandinfo always gets addedbz2009-10-031-1/+1
* Remove performance counter headers. This code came from NetBSD, but ourrpaulo2009-10-023-150/+0
* Promote the cpu_class local variable to global and expose it in md_var.hrpaulo2009-09-262-20/+23
* Add a new sysctl for reporting all of the supported page sizes.alc2009-09-181-0/+2
* Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating anphk2009-09-082-18/+57
* Reintroduce the r196640, after fixing the problem with my testing.kib2009-09-011-3/+0
* Reverse r196640 and r196644 for now.kib2009-08-291-0/+3
* Remove the altkstacks, instead instantiate threads with kernel stackkib2009-08-291-3/+0
* revert r196600; didn't notice it'd been done alreadysam2009-08-271-1/+0
* enable mesh by defaultsam2009-08-271-0/+1
* Introduce SheevaPlug support.raj2009-08-254-0/+234
* Exclude common Kirkwood settings so they can be shared among various platformsraj2009-08-254-8/+21
* Properly handle initial state of power mgmt.raj2009-08-253-2/+134
* Eliminate platform_pmap_init() to simplify Marvell bootstrap code.raj2009-08-255-44/+13
* KDB needs <machine/db_machdep.h>, so move it under #ifdef KDB.cognet2009-08-231-3/+2
* No need to remove the same flag multiple times.cognet2009-08-231-2/+2
* - Proprely intialize UART parameters at probe stage, so uart(4)stas2009-08-151-4/+4
* Use correct wbinv operation in pmap_l2cache_wbinv_range().raj2009-08-131-1/+1
* Merge the remainder of kern_vimage.c and vimage.h into vnet.c andrwatson2009-08-011-1/+0
* Add a new type of VM object: OBJT_SG. An OBJT_SG object is very similar tojhb2009-07-241-1/+1
* Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.raj2009-07-211-2/+2
* ARM pmap fixes.raj2009-07-203-5/+7
* Add IEEE80211_SUPPORT_MESH, following similar change to nanobsd andrpaulo2009-07-172-0/+2
* Add support to the virtual memory system for configuring machine-alc2009-07-122-2/+5
* Cleanup ALIGNED_POINTER:sam2009-07-051-0/+7
* Map DPCPU pages into ARM kernel VA space.raj2009-07-013-3/+11
* Correct the #endif comment.alc2009-06-261-1/+1
* Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/rwatson2009-06-262-5/+5
* This change is the next step in implementing the cache control functionalityalc2009-06-261-0/+35
* temporarily disable optional uarts; apparently we hang when probing themsam2009-06-251-9/+9
* Enable all populated TWSI (I2C) controllers on Marvell SOCs.raj2009-06-254-4/+9
* Fix typo.cognet2009-06-241-1/+1
* Fix typo.cognet2009-06-241-1/+1
* Introduce ata(4) support for Marvell integrated SATA controllers (found onraj2009-06-249-0/+958
* Implement a facility for dynamic per-cpu variables.jeff2009-06-239-1/+41
* Now that we have UARTs running with fast interrupt handlers the atasam2009-06-232-35/+208
* use consistent stylesam2009-06-231-1/+1
* kill left over cruftsam2009-06-221-2/+0
* enable optional GPS+RS485 uartssam2009-06-221-0/+14
* o add a bus space tag that forces a 2usec delay between r/w ops; this issam2009-06-224-11/+120
* fix typosam2009-06-221-1/+1
* o remove hack to write UUE+RTOIE in the uart's IER; force them with hintssam2009-06-223-21/+10
* hook arm_post_filter to ACK GPIO interrupts; this fixes the interruptsam2009-06-221-0/+8
* always define Cambria GPS+RS485 mappings as they are no longer conditionalsam2009-06-221-4/+0
* map the optional GPS and RS485 uart's on the Gateworks Cambria boardsam2009-06-222-21/+32
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