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* Implement pmap_clear_write().alc2006-07-201-0/+15
| | | | Discussed with: cognet@
* Fix ALT_BREAK_TO_DEBUGGER on the AT91 :cognet2006-07-201-5/+20
| | | | | | | | The core uart code expects the receive method to actually puts the characters read into its buffers. For AT91, it's done in the ipend routine, so also check if we have the alternate break sequence here. MFC after: 3 days
* Make sure we use REDUCE32 on the result of do_cksum(), as in_cksum_skip()cognet2006-07-181-2/+13
| | | | | | expects this. If we do not, this could result in wrong checksums. MFC after: 1 day
* If we can't defrag a packet, re-queue it instead of dropping it.cognet2006-07-171-1/+1
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* #if => #ifdefcognet2006-07-171-2/+2
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* at91_spi won't compile without spibus, so add it.cognet2006-07-171-0/+1
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* Oops bring back code that shouldn't have been removed by the previouscognet2006-07-151-0/+2
| | | | commit.
* Make sure that if uma_small_alloc() gets called recursively, we just give upcognet2006-07-151-7/+6
| | | | and call kmem_malloc(), to avoid a deadlock.
* Add a comment explaining why the OHCI mapping has been commented out.cognet2006-07-151-0/+9
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* MFp4: this now depends on new spi bus stuffimp2006-07-141-1/+3
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* MFp4: tweaksimp2006-07-141-7/+8
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* MFp4: elevate quality of slow clock a littleimp2006-07-141-1/+1
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* MFp4: paren policeimp2006-07-141-6/+4
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* MFp4:imp2006-07-143-8/+66
| | | | | | | | | | | | | | | Introduce framework to configure the multiplexed pins on boot. Since the USART supprots RS-485 multidrop mode, it allows the TX pins to float. However, for RS-232 operations, we don't want these pins to float. Instead, they should be pulled up to avoid mismatches. Linux does something similar when it configures the TX lines. This implies that we also allow the RX lines to float rather than be in the state they are left in by the boot loader. Since they are input pins, I think that this is the right thing to do. Plus minor for our board.
* MFp4:imp2006-07-141-1/+1
| | | | Fix typo in RTC_CALR_MK.
* The TSC board uses a 16MHz base clock for the AT91RM9200, while the Kwikbyteimp2006-07-141-0/+6
| | | | board uses a 10MHz base clock. Cope with this difference.
* Implement the set_time function. Rather pointless with this RTC, as itimp2006-07-141-3/+8
| | | | resets when the core resets, but there may be some use for it...
* MF p4:imp2006-07-143-319/+134
| | | | | Adapt to forthcoming spi framework. The ioctls for SPI commands and such belong in the higher level driver.
* Be sure to flush the cache after a partial read on timeout. Expandimp2006-07-141-3/+7
| | | | | comments about timeouts. Fix a style nit. Sometimes small messages were getting corrupted.
* Move some of the common parameters into the std. files for this platform.imp2006-07-143-11/+16
| | | | Also migrate from MD disk to NFS boot.
* Remove prototype for the undefined function counterhandler().cognet2006-07-141-1/+0
| | | | Submitted by: kevlo
* Add remote GDB bits for arm.cognet2006-07-142-0/+155
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* Simplify the pager support in DDB. Allowing different db commands tojhb2006-07-121-4/+2
| | | | | | | | | | | | | | | | install custom pager functions didn't actually happen in practice (they all just used the simple pager and passed in a local quit pointer). So, just hardcode the simple pager as the only pager and make it set a global db_pager_quit flag that db commands can check when the user hits 'q' (or a suitable variant) at the pager prompt. Also, now that it's easy to do so, enable paging by default for all ddb commands. Any command that wishes to honor the quit flag can do so by checking db_pager_quit. Note that the pager can also be effectively disabled by setting $lines to 0. Other fixes: - 'show idt' on i386 and pc98 now actually checks the quit flag and terminates early. - 'show intr' now actually checks the quit flag and terminates early.
* Comment out the mapping of the OHCI controller registers va == pa. Thiscognet2006-07-121-0/+2
| | | | | | address is in the userland address space. The proper thing is either to choose a virtual address in the kernel address space beyond the KVA, or to use pmap_mapdev().
* Add a new flag to pmap_enter_locked() to say if it's OK to wait. If it is, andcognet2006-07-111-10/+22
| | | | | | | | | we're unable to allocate the memory for a PTE, we'll wait until we can. If not, we'll just return. Use M_NOWAIT|M_USE_RESERVE to allocate PTEs, it is less aggressive than M_NOWAIT alone. Suggested by: alc
* Add support for configuring pins to be one of {GPIO, PERIPHERAL A orimp2006-07-023-1/+450
| | | | | PERIPHERAL B}, as well as direction of GPIO pin. Add defines for all the pins.
* MFp4:imp2006-07-021-53/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
* Backout previous commit, Warner committed at91_pio.c...cognet2006-06-231-1/+1
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* There's no need to allocate that much phdr/shdr from the stack.cognet2006-06-231-2/+2
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* Add the arm9_setup() prototype.cognet2006-06-231-0/+2
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* Comment out at91_pio.c, it's not in CVS.cognet2006-06-231-1/+1
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* arm9_setup() is now needed even if we're not using a gzipped kernel, so movecognet2006-06-221-1/+1
| | | | | | it outside the #ifdef KZIP Pointy Hat to: cognet
* Nitsville: the routine is called initarm, not init_arm, correct it inimp2006-06-211-1/+1
| | | | a comment.
* Don't forget to define uart_sa1110_vaddr.cognet2006-06-211-0/+2
| | | | Submitted by: kevlo
* Compute physmem so we can print it correctly on boot.imp2006-06-201-5/+5
| | | | Slightly optimize while I'm here.
* Probe the memory size of the board better. Look at the bus width,imp2006-06-202-2/+60
| | | | | | | | | | | number of banks, rows and columns the SDRAMC is programmed to access to determine the RAM size for the board, rather than hard-wiring it to be 32MB. My company's board with 64MB now probes correctly, as does the KB9202 with only 32MB. This means that to detect the right memory size, our boot loader must correctly initialize these values. This is a fairly safe assumption because the boot loader has to initialize SDRAM already, and it isn't really possible to change this register after we've accessed SDRAM.
* Make sure the stack is properly aligned.cognet2006-06-181-10/+32
| | | | Enable the MMU when relocating as well, and use write-through cache.
* comment out twi for now: no iicbus in KB920X: it breaks bootingimp2006-06-171-1/+1
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* Carefully note the RMII bit in the config register at attach time.imp2006-06-171-5/+9
| | | | | | | | The boot loader is supposed to leave this bit set to the right value for the board. If this bit was set at attach time, use it to init the config register correctly. Note: this means the boot loader has to properly initialize it.
* improve reporting of clocksimp2006-06-171-3/+2
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* Remove COMPAT_43 from GENERIC (and other kernel configs). For amd64 there'snetchild2006-06-154-4/+0
| | | | | | | | | | | | | | | | | | | | | | an explicit comment that it's needed for the linuxolator. This is not the case anymore. For all other architectures there was only a "KEEP THIS". I'm (and other people too) running a COMPAT_43-less kernel since it's not necessary anymore for the linuxolator. Roman is running such a kernel for a for longer time. No problems so far. And I doubt other (newer than ia32 or alpha) architectures really depend on it. This may result in a small performance increase for some workloads. If the removal of COMPAT_43 results in a not working program, please recompile it and all dependencies and try again before reporting a problem. The only place where COMPAT_43 is needed (as in: does not compile without it) is in the (outdated/not usable since too old) svr4 code. Note: this does not remove the COMPAT_43TTY option. Nagging by: rdivacky
* Remove mpte optimization from pmap_enter_quick().ups2006-06-151-4/+2
| | | | | | | | | There is a race with the current locking scheme and removing it should have no measurable performance impact. This fixes page faults leading to panics in pmap_enter_quick_locked() on amd64/i386. Reviewed by: alc,jhb,peter,ps
* MFp4:cognet2006-06-122-10/+139
| | | | | | | - Try hard to calculate a safe sp, so that the stack doesn't get smashed while uncompressing or relocating the kernel. - Bring in code needed to calculate the cacheline size etc, needed for arm9_idcache_wbinv_all.
* MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to becognet2006-06-121-1/+1
| | | | able to boot fat kernels.
* Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match thealc2006-06-111-6/+2
| | | | | | current interface with the machine-independent layer. Without this change, the page daemon would only have been awakened the first time that the number of pv entries went above the high water mark, not each time.
* Eliminate spl calls.alc2006-06-111-11/+0
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* Add a lock assertion. Remove dead (locking) code. Change some whitealc2006-06-101-36/+4
| | | | | | space. Reviewed by: cognet@
* Add pmap locking to pmap_extract().alc2006-06-091-4/+8
| | | | Tested by: cognet@
* Oops it seems I forgot to remove ARM32_NEW_VM_LAYOUT from here.cognet2006-06-073-3/+0
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* Add pmap locking to pmap_fault_fixup().alc2006-06-071-16/+7
| | | | | | Add an assertion to pmap_vac_me_harder(). Tested by: cognet@
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