| Commit message (Collapse) | Author | Age | Files | Lines |
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wired region. Rework the handling of unwire to do the it in batch,
both at pmap and object level.
All commits below are by alc.
MFC r268327:
Introduce pmap_unwire().
MFC r268591:
Implement pmap_unwire() for powerpc.
MFC r268776:
Implement pmap_unwire() for arm.
MFC r268806:
pmap_unwire(9) man page.
MFC r269134:
When unwiring a region of an address space, do not assume that the
underlying physical pages are mapped by the pmap. This fixes a leak
of the wired pages on the unwiring of the region mapped with no access
allowed.
MFC r269339:
In the implementation of the new function pmap_unwire(), the call to
MOEA64_PVO_TO_PTE() must be performed before any changes are made to the
PVO. Otherwise, MOEA64_PVO_TO_PTE() will panic.
MFC r269365:
Correct a long-standing problem in moea{,64}_pvo_enter() that was revealed
by the combination of r268591 and r269134: When we attempt to add the
wired attribute to an existing mapping, moea{,64}_pvo_enter() do nothing.
(They only set the wired attribute on newly created mappings.)
MFC r269433:
Handle wiring failures in vm_map_wire() with the new functions
pmap_unwire() and vm_object_unwire().
Retire vm_fault_{un,}wire(), since they are no longer used.
MFC r269438:
Rewrite a loop in vm_map_wire() so that gcc doesn't think that the variable
"rv" is uninitialized.
MFC r269485:
Retire pmap_change_wiring().
Reviewed by: alc
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by flag). The ia64 pmap.c changes are direct commit, since ia64 is
removed on head.
MFC r269368 (by alc):
Retire PVO_EXECUTABLE.
MFC r269728:
Change pmap_enter(9) interface to take flags parameter and superpage
mapping size (currently unused).
MFC r269759 (by alc):
Update the text of a KASSERT() to reflect the changes in r269728.
MFC r269822 (by alc):
Change {_,}pmap_allocpte() so that they look for the flag
PMAP_ENTER_NOSLEEP instead of M_NOWAIT/M_WAITOK when deciding whether
to sleep on page table page allocation.
MFC r270151 (by alc):
Replace KASSERT that no PV list locks are held with a conditional
unlock.
Reviewed by: alc
Approved by: re (gjb)
Sponsored by: The FreeBSD Foundation
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Rename vt_generate_vga_palette() to vt_generate_cons_palette() and
change it to build a palette where the color index is the same than in
terminal escape codes, not the VGA index. That's what TCHAR_CREATE()
uses and passes to vt(4).
The main differences between both orders are:
o Blue and red are swapped (1 <-> 4)
o Yellow and cyan are swapped (3 <-> 6)
The problem remained unnoticed, because the RGB bit indexes passed to
vt_generate_vga_palette() were reversed. This inversion was cancelled
by the colors inversions in the generated palette. For instance, red
(0xff0000) and blue (0x0000ff) have bytes in opposite order, but were
swapped in the palette. But after changing the value of blue (see last
paragraph), the modified color was in fact the red one.
While here, tune the palette to better match console colors and improve
the readability (especially the dark blue).
This is an MFC of r269783 and r269791.
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FreeBSD, historically, has always used 8-bit addresses for i2c devices
(7-bit device address << 1), always leaving the room for the read/write
bit.
This commit convert ti_i2c and revert r259127 on bcm2835_bsc to make them
compatible with 8-bit addresses. Previous to this commit an i2c device
would have different addresses depending on the controller it was attached
to (by example, when compared to any iicbb(4) based i2c controller), which
was a pretty annoying behavior.
Also, update the PMIC i2c address on beaglebone* DTS files to match the
new address scheme.
Now the userland utilities need to do the correct slave address shifting
(but it is going to work with any i2c controller on the system).
Discussed with: ian
MFC r267834:
Clarify the expected usage of I2C 7-bit slave addresses on ioctl(2)
interface.
While here add the cross reference to iic(4) on iicbus(4).
CR: D210
Suggested by: jmg
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Ignore IIC_ENOADDR from iicbus_reset() as it only means we have a
master-only controller.
This fixes the iic bus scan with i2c(8) (on supported controllers).
Tested with gpioiic(4).
MFC r267009:
Remove the unnecessary i2c slave address assignment.
The ti_i2c controller only works in the master mode and the i2c address
passed on iicbus_reset() is used to set the controller slave address when
operating as an i2c slave (which isn't currently supported).
When talking to a slave, the slave address is correctly provided to
ti_i2c_tranfer().
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Configure the analog input 7 which, on BBB, is connected to the 3V3B rail
through a voltage divisor (R163 and R164 on page 4 of BBB schematic).
Add a note about this on ti_adc(4) man page. The ti_adc(4) man page will
first appear on 10.1-RELEASE.
Suggested by: Sulev-Madis Silber (ketas)
Manual page reviewed by: brueffer (D127)
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Export two new settings for the AM335x PWM, the clock prescaler (clkdiv)
and the actual PWM frequency.
Enforce the maximum value for the period sysctl.
The frequency systcl now allows the direct setting of the PWM frequency
(it will try to find the better clkdiv and period for a given frequency,
i.e. the ones that will give the better PWM resolution).
This allows the use lower frequencies on the PWM. Without changing the
clock prescaler the minimum PWM frequency was 1.52kHz.
PWM frequencies checked with an osciloscope.
PWM output tested with some R/C servos at 50Hz.
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Cache the imx6 SoC type in a static var so that it only has to be figured
out by sniffing hardware registers once.
Add a missing clock register definition.
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Set ofwbus and simplebus to attach during BUS_PASS_BUS.
Define names that drivers can use to adjust their position relative to
other drivers within a BUS_PASS
Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that
a platform can attach some other bus first if necessary.
Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Attach arm generic interrupt and timer drivers in the middle of
BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.
Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass
device attachment on arm platforms. If this is defined, nexus attaches
early in BUS_PASS_BUS, and other busses and devices attach later, in the
pass number they are set up for. Without it defined, nexus attaches in
BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
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Add 64-bit atomic ops for armv6, and also for armv4 only in kernel code.
Use the new ops in the cddl code (and avoid defining functions with the
same names locally).
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Fix parsing of arch extensions in binutils/gas.
Use ".arch_extension sec" when compiling ARM TI code that uses the
security extensions.
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r269214, r269215, r269216, r269217, r269221:
busdma-v6 improvements, primarily:
- Allocate the temporary segments array per-map rather than per-tag.
- Avoid needlessly bouncing IO for mbufs and buffers allocated by
bus_dmamem_alloc() (in both situations we known they're allocated
on cacheline boundaries and don't need bouncing).
- Various minor reformatting and cleanups.
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Fix C++ exception handling for ARM EABI.
Just the part of r264070 that creates the FBSD_1.4 namespace in libc
is hand-applied, and then r264082 which creates the Versions.def entry
is MFC'd.
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Use unsigned compare against KERNBASE addr.
Use atomic ops on armv6.
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Pending interrupt status is cleared by writing to the ISR, not the data reg.
Use named constant rather than '0' to access the reset controller register.
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Map device memory using PTE_DEVICE attributes, and also ensure that the
shared flag is set on normal-memory mappings made via pmap_kenter() for SMP.
The "shared flag" part of this change isn't obvious from the diff, here's
the deal... by using the array of preformatted page table entry templates
instead of constructing the PTE from scratch, we automatically get the
right attribute bits set for both caching and shared.
Fix whitespace glitches.
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Add a page size field to struct vm_page.
Approved by: alc
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>r267146 | imp | 2014-06-05 22:08:55 -0600 (Thu, 05 Jun 2014) | 4 lines
>Restore comments accidentally removed.
>r263749 | imp | 2014-03-25 16:08:31 -0600 (Tue, 25 Mar 2014) | 18 lines
>Rather than require a makeoptions DEBUG to get debug correct,
>add it in kern.mk, but only if we're using clang. While this
>option is supported by both clang and gcc, in the future there
>may be changes to clang which change the defaults that require
>a tweak to build our kernel such that other tools in our tree
>will work. Set a good example by forcing -gdwarf-2 only for
>clang builds, and only if the user hasn't specified another
>dwarf level already. Update UPDATING to reflect the changed
>state of affairs. This also keeps us from having to update
>all the ARM kernels to add this, and also keeps us from
>in the future having to update all the MIPS kernels and is
>one less place the user will have to know to do something
>special for clang and one less thing developers will need
>to do when moving an architecture to clang.
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Fixes to the ti_sdhci and sdhci drivers (fix clock divisor calcs).
Use the ti_sdhci driver instead of ti_mmchs for Pandaboard.
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Make sure the PCB is aligned on 8 bytes, we may use ldrd/strd to access it,
which may have strong alignment requirements.
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Fix an itt instruction. We need to execute both the mov and b instructions
when building for Thumb.
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- Fix a typo.
- Use bus_dmamap_unload(), it is not optional.
- The new allocator won't return coherent memory for any size > PAGE_SIZE,
so don't assume we have coherent memory, and explicitely use
bus_dmamap_sync().
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Interrupts need to be disabled on entry to cpu_sleep() for ARM. Given
that and the need to be in a critical section when switching to idleclock
mode for event timers, use spinlock_enter()/exit() to achieve both needs.
Clean up some style nits.
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Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
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Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of
the common locore.S file and into the mv/armadaxp directory.
Consolidate all the AP core startup stuff under a single #ifdef SMP block
Call idcache_inv_all from the AP core entry code before turning on the MMU.
Also, enable instruction and branch caches, which should be safe now that
they're properly initialized/invalidated first.
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Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.
Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.
Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.
Add defines for the bits in the PL310 debug control register.
Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
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Omit from the universe build all config files tagged with #NO_UNIVERSE.
Add FDT to the VYBRID kernel.
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Add SMP support for Zedboard.
Use edge-triggered interrupts rather than polling loops to avoid missing
transitions of the INIT_B line. Also, release the mutex during uiomove().
Convert the Zynq SoC support to the new routines for static device mapping.
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There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.
Flush and invalidate caches on each CPU as part of handling IPI_STOP.
Don't use multiprocessing-extensions instruction on processors that don't
support SMP.
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Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.
Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).
Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.
Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)
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Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead
define a few imx_ccm_foo() functions that are implemented by the imx51
or imx6 ccm code.
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* Define support for the SDHCI driver, although it doesn't work yet
* Fix the memory mappings for IPU
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Tell VM we now have ARM platforms with physically discontiguous memory.
Define the full 1024M of ram on the imx51 and imx53 boards.
Use a more professional uart device description.
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Follow files.imx51 and add vt support for imx53.
Add fsl,imx53 compatible string.
Need to include machine/fdt.h in vt_early_fb.c
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