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* Add missing "struct" in i386/i386/machdep.c,v 1.497 by deischen@.ru2005-11-241-1/+1
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* Use a magic number to know we were started from the elf wrapper.cognet2005-11-243-9/+24
| | | | Add a dummy _start function to make the non-elf version of the wrapper work.
* MFP4: Bring in arm9 cache-related functionscognet2005-11-231-50/+169
| | | | Obtained from: NetBSD
* Force pmap to write-back the pte cacheline after each pte modification,cognet2005-11-211-0/+5
| | | | | even if the pte is supposed to be cached in write through mode (might be a skyeye bug, I'll have to check).
* Add an alternate ID for the arm920t (the real solution is to havecognet2005-11-212-0/+3
| | | | per-cpu class masks, but oh well).
* Eliminate pmap_init2(). It's no longer used.alc2005-11-201-5/+0
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* There's no need to include <machine/asmacros.h> here.cognet2005-11-081-1/+0
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* MFi386 rev 1.536 (sort of)cognet2005-11-063-30/+24
| | | | | | | | Move what can be moved (UMA zones creation, pv_entry_* initialization) from pmap_init2() to pmap_init(). Create a new function, pmap_postinit(), called from cpu_startup(), to do the L1 tables allocation. pmap_init2() is now empty for arm as well.
* Normalize a significant number of kernel malloc type names:rwatson2005-10-311-1/+1
| | | | | | | | | | | | | | | | | | | - Prefer '_' to ' ', as it results in more easily parsed results in memory monitoring tools such as vmstat. - Remove punctuation that is incompatible with using memory type names as file names, such as '/' characters. - Disambiguate some collisions by adding subsystem prefixes to some memory types. - Generally prefer lower case to upper case. - If the same type is defined in multiple architecture directories, attempt to use the same name in additional cases. Not all instances were caught in this change, so more work is required to finish this conversion. Similar changes are required for UMA zone names.
* Reorganize the interrupt handling code a bit to make a few things cleanerjhb2005-10-251-22/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and increase flexibility to allow various different approaches to be tried in the future. - Split struct ithd up into two pieces. struct intr_event holds the list of interrupt handlers associated with interrupt sources. struct intr_thread contains the data relative to an interrupt thread. Currently we still provide a 1:1 relationship of events to threads with the exception that events only have an associated thread if there is at least one threaded interrupt handler attached to the event. This means that on x86 we no longer have 4 bazillion interrupt threads with no handlers. It also means that interrupt events with only INTR_FAST handlers no longer have an associated thread either. - Renamed struct intrhand to struct intr_handler to follow the struct intr_foo naming convention. This did require renaming the powerpc MD struct intr_handler to struct ppc_intr_handler. - INTR_FAST no longer implies INTR_EXCL on all architectures except for powerpc. This means that multiple INTR_FAST handlers can attach to the same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach to the same interrupt. Sharing INTR_FAST handlers may not always be desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun either. Drivers can always still use INTR_EXCL to ask for an interrupt exclusively. The way this sharing works is that when an interrupt comes in, all the INTR_FAST handlers are executed first, and if any threaded handlers exist, the interrupt thread is scheduled afterwards. This type of layout also makes it possible to investigate using interrupt filters ala OS X where the filter determines whether or not its companion threaded handler should run. - Aside from the INTR_FAST changes above, the impact on MD interrupt code is mostly just 's/ithread/intr_event/'. - A new MI ddb command 'show intrs' walks the list of interrupt events dumping their state. It also has a '/v' verbose switch which dumps info about all of the handlers attached to each event. - We currently don't destroy an interrupt thread when the last threaded handler is removed because it would suck for things like ppbus(8)'s braindead behavior. The code is present, though, it is just under #if 0 for now. - Move the code to actually execute the threaded handlers for an interrrupt event into a separate function so that ithread_loop() becomes more readable. Previously this code was all in the middle of ithread_loop() and indented halfway across the screen. - Made struct intr_thread private to kern_intr.c and replaced td_ithd with a thread private flag TDP_ITHREAD. - In statclock, check curthread against idlethread directly rather than curthread's proc against idlethread's proc. (Not really related to intr changes) Tested on: alpha, amd64, i386, sparc64 Tested on: arm, ia64 (older version of patch by cognet and marcel)
* Unbreak for !__XSCALE__.cognet2005-10-233-0/+5
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* Cleanup.cognet2005-10-201-13/+1
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* Use the clock count register as a timecounter, as it's more accurate.cognet2005-10-171-16/+13
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* Whitespace.jhb2005-10-141-1/+1
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* Change the userland atomic operations on arm to use memory operands forjhb2005-10-141-16/+22
| | | | | | | | | the modified memory rather than using register operands that held a pointer to the memory. The biggest effect is that we now correctly tell the compiler that these functions change the memory that these functions modify. Reviewed by: cognet
* 1. Change prototype of trapsignal and sendsig to use ksiginfo_t *, mostdavidxu2005-10-143-22/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | changes in MD code are trivial, before this change, trapsignal and sendsig use discrete parameters, now they uses member fields of ksiginfo_t structure. For sendsig, this change allows us to pass POSIX realtime signal value to user code. 2. Remove cpu_thread_siginfo, it is no longer needed because we now always generate ksiginfo_t data and feed it to libpthread. 3. Add p_sigqueue to proc structure to hold shared signals which were blocked by all threads in the proc. 4. Add td_sigqueue to thread structure to hold all signals delivered to thread. 5. i386 and amd64 now return POSIX standard si_code, other arches will be fixed. 6. In this sigqueue implementation, pending signal set is kept as before, an extra siginfo list holds additional siginfo_t data for signals. kernel code uses psignal() still behavior as before, it won't be failed even under memory pressure, only exception is when deleting a signal, we should call sigqueue_delete to remove signal from sigqueue but not SIGDELSET. Current there is no kernel code will deliver a signal with additional data, so kernel should be as stable as before, a ksiginfo can carry more information, for example, allow signal to be delivered but throw away siginfo data if memory is not enough. SIGKILL and SIGSTOP have fast path in sigqueue_add, because they can not be caught or masked. The sigqueue() syscall allows user code to queue a signal to target process, if resource is unavailable, EAGAIN will be returned as specification said. Just before thread exits, signal queue memory will be freed by sigqueue_flush. Current, all signals are allowed to be queued, not only realtime signals. Earlier patch reviewed by: jhb, deischen Tested on: i386, amd64
* Export PAGE_SIZE from genassym.c, and include assym.s in bcopy_page.S,cognet2005-10-062-1/+5
| | | | instead of <machine/param.h>.
* Remove a never reached RET.cognet2005-10-041-1/+0
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* strd needs the destination to be double-word aligned, but the pointer passedcognet2005-10-041-6/+0
| | | | | to savectx isn't always, so always use stmia, savectx isn't called enough to need that kind of optimization.
* dump_avail has nothing to do with ARM_USE_SMALL_ALLOC, so move itscognet2005-10-041-1/+1
| | | | declaration out of the #ifdef.
* Remove duplicate entry for DDB.cognet2005-10-042-2/+0
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* Fix build when DDB isn't defined.cognet2005-10-041-0/+2
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* Bring in the good version of this file.cognet2005-10-031-44/+2
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* Add dma and aau.cognet2005-10-031-0/+2
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* Import dummy drivers for the i80321 DMA controller and AAU.cognet2005-10-035-2/+628
| | | | | | The DMA controller driver only knows how to do memory to memory copies, and the AAU driver how to zero a chunk of memory. Use them to process big (>=1KB) copying/zeroing.
* Make mem.c know about the pages allocated with ARM_USE_SMALL_ALLOC.cognet2005-10-031-2/+12
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* Export the variables needed for the copy/zero API.cognet2005-10-031-0/+5
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* Make sure the interrupt is masked before processing it, or bad thingscognet2005-10-031-3/+3
| | | | can happen.
* If a thread already tries to allocate a new memory range, wait for itcognet2005-10-031-7/+22
| | | | instead of trying to do the same.
* Provide a dump_avail[] variable, which contains the page ranges to becognet2005-10-033-14/+39
| | | | | | | dumped. For iq31244_machdep.c, attempt to recognize hints provided by the elf trampoline.
* - Provide the kernel l1pt physical address, for userland.cognet2005-10-031-13/+54
| | | | | | | - Use the new API for pmap_copy_page() and pmap_zero_page(). - Just write-back the pages in pmap_qenter(), and invalidate it in pmap_qremove(). - Nuke the cache flushing in pmap_enter_quick(), it's not needed anymore.
* Add a new API to let platform-specific ports provide functions for bigcognet2005-10-034-0/+159
| | | | copy/zeroing.
* Export the virtual and physical address in which the kernel was loaded,cognet2005-10-031-2/+9
| | | | needed for userland when reading kernel dumps.
* Import a small ELF trampoline, in which the kernel is embedded, and thatcognet2005-10-032-0/+233
| | | | | | is able to load the kernel into memory, symbol table included. This is needed to be able to access the symbol table from DDB without a boot loader.
* *blush*cognet2005-10-031-4/+47
| | | | | | Don't try to dereference map if it's NULL. While I'm there, increase the minimum value to write-back/invalidate the whole dcache in bus_dmamap_sync().
* Only save the registers that are used.cognet2005-10-031-2/+2
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* asm versions of in_cksum_hdr() and in_pseudo().cognet2005-10-032-14/+80
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* Implement savectx().cognet2005-10-031-0/+15
| | | | Obtained from: NetBSD
* Kernel dump for arm, ripped from the ia64/amd64 version.cognet2005-10-031-15/+353
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* Add a new atomic_fetchadd() primitive that atomically adds a value to ajhb2005-09-271-0/+38
| | | | | | | | | variable and returns the previous value of the variable. Tested on: i386, alpha, sparc64, arm (cognet) Reviewed by: arch@ Submitted by: cognet (arm) MFC after: 1 week
* Fix multiple abuses of __RMAN_RESOURCE_VISIBLE in the arm code.cognet2005-09-259-44/+55
| | | | Spotted out by: phk
* Move the prototypes of db_md_set_watchpoint(), db_md_clr_watchpoint()marcel2005-09-101-3/+0
| | | | and db_md_list_watchpoints() to ddb/ddb.h.
* Pass a value of type vm_prot_t to pmap_enter_quick() so that it determinealc2005-09-031-3/+3
| | | | whether the mapping should permit execute access.
* Move MINSIGSTKSZ from <machine/signal.h> to <machine/_limits.h> and renamestefanf2005-08-202-4/+3
| | | | | | | | | | it to __MINSIGSTKSZ. Define MINSIGSTKSZ in <sys/signal.h>. This is done in order to use MINSIGSTKSZ for the macro PTHREAD_STACK_MIN in <pthread.h> (soon <limits.h>) without having to include the whole <sys/signal.h> header. Discussed with: bde
* - Add support for saving stack traces and displaying them via printf(9)jeff2005-08-031-0/+19
| | | | | | | and KTR. Contributed by: Antoine Brodin <antoine.brodin@laposte.net> Concept code from: Neal Fachan <neal@isilon.com>
* msdosfs_conv.c references cmos_wall_clock and adjkerntz. Since theseimp2005-07-271-0/+3
| | | | | are 0 for arm, define them as such to make msdosfs_conv.c compile again on arm.
* Add extra constraints to tell the compiler that the memory be modifiedjhb2005-07-271-2/+4
| | | | | | | | | | | | in the arm __swp() and sparc64 casa() and casax() functions is actually being used as an input and output and not just the value of the register that points to the memory location. This was the underlying source of the mbuf refcount problems on sparc64 a while back. For arm this should be a nop because __swp() has a constraint to clobber all memory which can probably be removed now. Reviewed by: alc, cognet MFC after: 1 week
* Use a + constraint modifier for a register arg in __bswap16_var().jhb2005-07-271-3/+2
| | | | Reviewed by: cognet
* Convert the atomic_ptr() operations over to operating on uintptr_tjhb2005-07-151-8/+4
| | | | | | | | | | variables rather than void * variables. This makes it easier and simpler to get asm constraints and volatile keywords correct. MFC after: 3 days Tested on: i386, alpha, sparc64 Compiled on: ia64, powerpc, amd64 Kernel toolchain busted on: arm
* Validate if the value written into {FS,GS}.base is a canonicaldavidxu2005-07-101-1/+2
| | | | | | | | | address, writting non-canonical address can cause kernel a panic, by restricting base values to 0..VM_MAXUSER_ADDRESS, ensuring only canonical values get written to the registers. Reviewed by: peter, Josepha Koshy < joseph.koshy at gmail dot com > Approved by: re (scottl)
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