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* Enable SCTP, since it is also enabled on GENERIC and it works fine ontuexen2013-07-011-0/+1
| | | | | | the Raspberry Pi. Discussed with: rpaulo
* The mbox driver is actually MP safe, so set the right flag inrpaulo2013-07-011-5/+3
| | | | bus_setup_intr().
* Disable debugging.rpaulo2013-07-011-2/+0
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* Use the new FDT_FILE rpi.dts.rpaulo2013-07-011-1/+1
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* Fix issues with zeroing and fetching the counters, on x86 and ppc64.kib2013-07-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues were noted by Bruce Evans and are present on all architectures. On i386, a counter fetch should use atomic read of 64bit value, otherwise carry from the increment on other CPU could be lost for the given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not available on the machine, it cannot be SMP and it is enough to disable preemption around read to avoid the split read. On x86 the counter increment is not atomic on purpose, which makes it possible for the store of the incremented result to override just zeroed per-cpu slot. The effect would be a counter going off by arbitrary value after zeroing. Perform the counter zeroing on the same processor which does the increments, making the operations mutually exclusive. On i386, same as for the fetching, if the cmpxchg8b is not available, machine is not SMP and we disable preemption for zeroing. PowerPC64 is treated the same as amd64. For other architectures, the changes made to allow the compilation to succeed, without fixing the issues with zeroing or fetching. It should be possible to handle them by using the 64bit loads and stores atomic WRT preemption (assuming the architectures also converted from using critical sections to proper asm). If architecture does not provide the facility, using global (spin) mutex would be non-optimal but working solution. Noted by: bde Sponsored by: The FreeBSD Foundation
* Add INET6.rpaulo2013-06-301-0/+1
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* Replace some spaces to tab.ray2013-06-301-4/+4
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* Decrypt magic numbers - define names for fields of Generic Timer's CNTKCTL reg.ray2013-06-301-3/+23
| | | | Submitted by: Ruslan Bukin <br@bsdpad.com>
* In generic_bs_map(), use kmem_alloc_nofault() instead of kmem_alloc(), as wecognet2013-06-301-1/+1
| | | | | | only need virtual addresses. Submitted by: alc
* Arndale Board (by Insignal) kernel config file.ray2013-06-291-0/+135
| | | | | | | More info on the Wiki page https://wiki.freebsd.org/FreeBSD/arm/ArndaleBoard Submitted by: Ruslan Bukin <br@bsdpad.com> Reviewed by: gonzo
* - Fix IMAPx registers values calculationgonzo2013-06-291-20/+24
| | | | | | | | | - Initialize SMAPx registers too although they're unused in QEMU - Do not pass IO/MEM resources to upper bus for activation, handle them locally. Previously ACTIVATE method of upper bus was no-op so nothing bad happened. But now FDT maps physaddr to vaddr and it causes troubles: fdtbus_activate_resource resource assumes that bustag/bushandle are already set which in this case is wrong.
* Enable patth-through of IRQ30 and IRQ31 to PIC just as comment statesgonzo2013-06-291-1/+1
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* Import basic support for Samsung Exynos 5 support.ray2013-06-2910-0/+1480
| | | | | Submitted by: Ruslan Bukin <br@bsdpad.com> Reviewed by: gonzo
* Add ARM Generic Timer driver.ray2013-06-291-0/+374
| | | | Submitted by: Ruslan Bukin <br@bsdpad.com>
* o Initialize interrupt groups as Group 0 (secure interrupts).ray2013-06-291-15/+29
| | | | | | o Minor cleanup. Submitted by: Ruslan Bukin <br@bsdpad.com>
* Bump max number of IRQs for Cortex-Ax family to cover Exynos5 requirement.ray2013-06-281-1/+1
| | | | Submitted by: Ruslan Bukin <br@bsdpad.com>
* Add identification for Cortex-A15 (R0) cores.ray2013-06-283-1/+5
| | | | Submitted by: Ruslan Bukin <br@bsdpad.com>
* Support reading registers r0-r3 when unwinding. There is a seperateandrew2013-06-271-0/+19
| | | | | instruction to load these. We only hit it when unwinding past an trap frame as in C r0-r3 would never have been saved onto the stack.
* Add UNWINDSVCFRAME to provide the unwind pseudo ops to allow us to unwindandrew2013-06-272-2/+11
| | | | | | | past a trapframe. Use this macro in exception_exit as it is the function the unwinder enters as the functions that store the frame setting lr to point to it.
* - Request non-cached memory for framebuffergonzo2013-06-271-2/+24
| | | | - Properly probe/initialize syscons
* Print the 'setting internal ...' message only with bootverbose.rpaulo2013-06-261-1/+3
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* Make support for atomics on ARM complete.ed2013-06-151-42/+316
| | | | | | | | | Provide both __sync_*-style and __atomic_*-style functions that perform the atomic operations on ARMv5 by using Restartable Atomic Sequences. While there, clean up some pieces of code where it's sufficient to use regular uint32_t to store register contents and don't need full reg_t's. Also sync this back to the MIPS code.
* Fix the vfp code to work with the 16 register variants of the VFP unit. Weandrew2013-06-132-35/+46
| | | | | | | | check which variant we are on, and if it is a VFPv3 or v4, and has 32 double registers we save these. This fixes VFP support on Raspberry Pi. While here clean fmrx and fmxr up to use the register names from vfp.h as opposed to the raw register names.
* Add C11 atomic fallbacks for ARM.ed2013-06-131-0/+540
| | | | | | | | | | | | | | | | | | Basically the situation is as follows: - When using Clang + armv6, we should not need any intrinsics. It should support it, even though due to a target misconfiguration it does not. We should fix this in Clang. - When using Clang + noarmv6, provide __atomic_* functions that disable interrupts. - When using GCC + armv6, we can provide __sync_* intrinsics, similar to what we did for MIPS. As ARM and MIPS are quite similar, simply base this implementation on the one I did for MIPS. - When using GCC + noarmv6, disable the interrupts, like we do for Clang. This implementation still lacks functions for noarmv6 userspace. To be done.
* Increase the maximum KVM available on TI chips. Not sure why we suddenly needcognet2013-06-091-3/+3
| | | | that much, but that lets me boot with 1GB of RAM.
* Merge in changes from NetBSD:andrew2013-06-081-17/+25
| | | | | | * Remove support for non-elf files. * Add the VFP setjmp magic numbers. * Add the offsets for the VFP registers within the buffer.
* Reduce the difference to NetBSD.andrew2013-06-071-25/+27
| | | | | | | | | | | | * Stop pretending we support anything other than ELF by removing code surrounded by #ifdef __ELF__ ... #endif. * Remove _JB_MAGIC_SETJMP and _JB_MAGIC__SETJMP, they are defined in setjmp.h, which is able to be included from asm. * Fix the spelling of dependent. * Rename END _END and add END and ASEND to complement ENTRY and ASENTRY respectively * Add macros to simplify accessing the Global Offset Table, some of these will be used in the upcoming update to the setjmp functions.
* Fix the passing of time on Armada XP.gber2013-06-042-1/+12
| | | | | | | In order to become independent of Coherency Fabric frequency, configure Timer and Watchdog to operate in 25MHz mode. Submitted by: Zbigniew Bodek <zbb@semihalf.com>
* Implement pmap_copy() for ARMv6/v7.gber2013-06-041-0/+120
| | | | | | | | Copy the given range of mappings from the source map to the destination map, thereby reducing the number of VM faults on fork. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
* AM335x LCD controller driver with syscons supportgonzo2013-05-274-0/+1518
| | | | | | Limitations: - Raster mode only - 24 and 32 bpp only
* Add PWM module driver for AM335x. Only eCAS subsystem is supportedgonzo2013-05-273-0/+319
| | | | | Export function to configure eCAS submodule from another drivers. It's used to control LCD panel backlight on AM335x EVM.
* Add SCM registers definitions for AM335x platformgonzo2013-05-271-0/+38
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* Add clock definitions for LCD controller and PWM modulegonzo2013-05-272-3/+99
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* Rework and organize pmap_enter_locked() function.gber2013-05-231-86/+72
| | | | | | | | | | pmap_enter_locked() implementation was very ambiguous and confusing. Rearrange it so that each part of the mapping creation is separated. Avoid walking through the redundant conditions. Extract vector_page specific PTE setup from normal PTE setting. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
* Stop using PVF_MOD, PVF_REF & PVF_EXEC flags in pv_entry, use PTE.gber2013-05-232-36/+33
| | | | | | | | | | | | | Using PVF_MOD, PVF_REF and PVF_EXEC is redundant as we can get the proper info from PTE bits. When the mapping is marked as executable and has been referenced we assume that it has been executed. Similarly, when the mapping is set to be writable and is referenced, it must have been due to write access to it. PVF_MOD and PVF_REF flags are kept just for pmap_clearbit() usage, to pass the information on which bit should be cleared. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
* Improve, optimize and clean-up ARMv6/v7 memory management related code.gber2013-05-234-222/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use pmap_find_pv if needed instead of multiplying its code throughout pmap-v6. Avoid possible NULL pointer dereference in pmap_enter_locked() When trying to get m->md.pv_memattr, make sure that m != NULL, in particular that vector_page is set to be NULL. Do not set PGA_REFERENCED flag in pmap_enter_pv(). On ARM any new page reference will result in either entering the new mapping by calling pmap_enter, etc. or fixing-up the existing mapping in pmap_fault_fixup(). Therefore we set PGA_REFERENCED flag in the earlier mentioned cases and setting it later in pmap_enter_pv() is just waste of cycles. Delete unused pm_pdir pointer from the pmap structure. Rearrange brackets in the fault cause detection in trap.c Place the brackets correctly in order to see course of the conditions instantaneously. Unify naming in pmap-v6.c and improve style Use naming common for whole pmap and compatible with other pmaps, improve style where possible: pm -> pmap pg -> m opg -> om *pt -> *ptep *pte -> *ptep *pde -> *pdep Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
* Switch to AP[2:1] access permissions model. Store "referenced"gber2013-05-235-111/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | bit in PTE. Enable Access Flag in CPU control. With AF enabled each valid mapping needs to have referenced bit in PTE set in order to be able to cache it in the TLB. AP[0] bit is to be used as reference flag. All access permissions are encoded by AP[2:1] wherein AP[1] is in fact "user enable" and AP[2](APX) is "write disable". All mappings are always set to be valid. Reference emulation is performed by setting/clearing reference flag in PTE. md.pvh_attrs are no longer necessary however pv_flags are still being used for now. Marking vm_page as "dirty" or "referenced" is being performed on: - page or flag fault servicing in pmap_fault_fixup(), basing on the fault type - vm_fault servicing in pmap_enter() according to the desired protections and faulty access type Redundant page marking has been removed as on ARM we know exactly when the particular page is referenced or is going to be written. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Sponsored by: The FreeBSD Foundation, Semihalf
* o Relax locking assertions for vm_page_find_least()attilio2013-05-212-0/+4
| | | | | | | | | | | | o Relax locking assertions for pmap_enter_object() and add them also to architectures that currently don't have any o Introduce VM_OBJECT_LOCK_DOWNGRADE() which is basically a downgrade operation on the per-object rwlock o Use all the mechanisms above to make vm_map_pmap_enter() to work mostl of the times only with readlocks. Sponsored by: EMC / Isilon storage division Reviewed by: alc
* Add a comment explaining why stack_capture is empty for EABI and clang.andrew2013-05-191-0/+12
| | | | | | While here add a comment pointing out that, while r11 is not the frame pointer on EABI as there is no frame pointer, it's value is unused so is safe.
* Back out r250768 until I can further investigate why it mightkientzle2013-05-181-1/+1
| | | | be causing problems with the BeagleBone Black boot.
* Label the mmc child after the parent.kientzle2013-05-181-1/+1
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* Revert r250692. We'll use 1 kernel config file for the BeagleBone models.rpaulo2013-05-172-128/+3
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* Fix L2 cache write-back invalidate for Sheeva core.gber2013-05-161-0/+8
| | | | | Submitted by: Michal Dubiel Obtained from: Netasq, Semihalf
* Add a kernel config file for the BeableBone Black SoC.rpaulo2013-05-161-0/+127
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* Port the new PV entry allocator from amd64/i386/mips to armv6/v7.gber2013-05-142-79/+470
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PV entries are now roughly half the size. Instead of using a shared UMA zone for 28 byte pv entries (two 8-byte tailq nodes, a 4 byte pointer, a 4 byte address and 4 byte flags), we allocate a page at a time per process. This provides 252 pv entries per process (actually, per pmap address space) and eliminates one of the 8-byte tailq entries since we now can track per-process pv entries implicitly. The pointer to the pmap can be eliminated by doing address arithmetic to find the metadata on the page headers to find a single pointer shared by all 252 entries. There is an 8-int bitmap for the freelist of those 252 entries. When in serious low memory condition, allocation of another pv_chunk is possible by freeing some pages in pmap_pv_reclaim(). Added pv_entry/pv_chunk related statistics to pmap. pv_entry/pv_chunk statistics can be accessed via sysctl vm.pmap. Ported PTE freelist of KVA allocation and maintenance from i386. Using an idea from Stephan Uphoff, use the empty pte's that correspond to the unused kva in the pv memory block to thread a freelist through. This allows us to free pages that used to be used for pv entry chunks since we can now track holes in the kva memory block. As both ARM pmap.c and pmap-v6.c use the same header and pv_entry, pmap and md_page structures are different, it was needed to separate code designed for ARMv6/7 from the one for other ARMs. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Reviewed by: alc Sponsored by: The FreeBSD Foundation, Semihalf
* Tidy up some CVS workarounds.peter2013-05-122-2/+0
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* Don't use the old stack-walking code withkientzle2013-05-111-4/+5
| | | | | | | | | | | | | | | | | | EABI ARM kernels or clang-compiled ARM kernels. This fixes a crash seen in clang-compiled ARM kernels that include WITNESS. This code could be easily modified to walk the stack for current clang-generated code (including EABI) but Andrew Turner has raised concerns that the stack frame currently emitted by clang isn't actually required by EABI so such a change might cause problems down the road. In case anyone wants to experiment, the change to support current clang-compiled kernels involves simply setting FR_RFP=0 and FR_SCP=1.
* Update copyright date.ray2013-05-0824-23/+24
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* Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h inattilio2013-05-072-7/+4
| | | | | | | | | order to match the MAXCPU concept. The change should also be useful for consolidation and consistency. Sponsored by: EMC / Isilon storage division Obtained from: jeff Reviewed by: alc
* decode_win_sdram_fixup() function should be declared, defined and usedgber2013-05-071-0/+4
| | | | | | only by Armada XP Obtained from: Semihalf
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