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* - Proprely intialize UART parameters at probe stage, so uart(4)stas2009-08-151-4/+4
| | | | | | | | | will initialize the FIFO memory correctly on attach. Before that this values was intialized in only in at91_usart_bus_attach which is called after the uart(4) memory allocation happens. Approved by: re (kib) MFC after: 1 week
* Use correct wbinv operation in pmap_l2cache_wbinv_range().raj2009-08-131-1/+1
| | | | | | | Submitted by: Michal Hajduk Reviewed by: stas Approved by: re (kib) Obtained from: Semihalf
* Merge the remainder of kern_vimage.c and vimage.h into vnet.c andrwatson2009-08-011-1/+0
| | | | | | | | | | vnet.h, we now use jails (rather than vimages) as the abstraction for virtualization management, and what remained was specific to virtual network stacks. Minor cleanups are done in the process, and comments updated to reflect these changes. Reviewed by: bz Approved by: re (vimage blanket)
* Add a new type of VM object: OBJT_SG. An OBJT_SG object is very similar tojhb2009-07-241-1/+1
| | | | | | | | | | | a device pager (OBJT_DEVICE) object in that it uses fictitious pages to provide aliases to other memory addresses. The primary difference is that it uses an sglist(9) to determine the physical addresses for a given offset into the object instead of invoking the d_mmap() method in a device driver. Reviewed by: alc Approved by: re (kensmith) MFC after: 2 weeks
* Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.raj2009-07-211-2/+2
| | | | | | | | | | On some ARM variations CPU func dispatcher has the D-cache invalidate method point to write-back invalidate, which is wrong, and can lead to a crash/panic on affected platforms. Spotted by: HPS Reviewed by: cognet Approved by: re (kib)
* ARM pmap fixes.raj2009-07-203-5/+7
| | | | | | | | | | | | | | | | | | | a) nocache-remap problem When a page is remapped into a non-cacheable virtual memory region there was no associated write-back invalidate operation performed. We remove writeback of the original buffer size from bus_dmamem_alloc() and add appropriate L1/L2 flush operation. b) missing write-back invalidate operation In pmap_kremove a page is removed so we must do a write-back invalidate operation aligned to the page virtual address. Submitted by: Michal Hajduk Reviewed by: Mark Tinguely, rpaulo, stas Approved by: re (kib) Obtained from: Semihalf
* Add IEEE80211_SUPPORT_MESH, following similar change to nanobsd andrpaulo2009-07-172-0/+2
| | | | | | other GENERIC kernels. Approved by: re (kib)
* Add support to the virtual memory system for configuring machine-alc2009-07-122-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib)
* Cleanup ALIGNED_POINTER:sam2009-07-051-0/+7
| | | | | | | | | | | o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v) o define as "1" on amd64 and i386 where there is no restriction o make the type returned consistent with ALIGN o remove _ALIGNED_POINTER o make associated comments consistent Reviewed by: bde, imp, marcel Approved by: re (kensmith)
* Map DPCPU pages into ARM kernel VA space.raj2009-07-013-3/+11
| | | | | | | | | | | DPCPU area was not properly mapped into kernel VA space, which caused page fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU area into kernel VA space. Submitted by: Michal Hajduk, Piotr Ziecik Reviewed by: cognet, stas Approved by: re (kib) Obtained from: Semihalf
* Correct the #endif comment.alc2009-06-261-1/+1
| | | | | Noticed by: jmallett Approved by: re (kib)
* Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/rwatson2009-06-262-5/+5
| | | | | | | | | | | | | IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
* This change is the next step in implementing the cache control functionalityalc2009-06-261-0/+35
| | | | | | | | | | | required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb
* temporarily disable optional uarts; apparently we hang when probing themsam2009-06-251-9/+9
| | | | (and they are not present)
* Enable all populated TWSI (I2C) controllers on Marvell SOCs.raj2009-06-254-4/+9
| | | | Obtained from: Semihalf
* Fix typo.cognet2009-06-241-1/+1
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* Fix typo.cognet2009-06-241-1/+1
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* Introduce ata(4) support for Marvell integrated SATA controllers (found onraj2009-06-249-0/+958
| | | | | | | 88F5xxx, 88F6xxx and MV78xxx system on chip devices). Reviewed by: stas Obtained from: Semihalf
* Implement a facility for dynamic per-cpu variables.jeff2009-06-239-1/+41
| | | | | | | | | | | | | | | - Modules and kernel code alike may use DPCPU_DEFINE(), DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined PCPU_*. Requires only one extra instruction more than PCPU_* and is virtually the same as __thread for builtin and much faster for shared objects. DPCPU variables can be initialized when defined. - Modules are supported by relocating the module's per-cpu linker set over space reserved in the kernel. Modules may fail to load if there is insufficient space available. - Track space available for modules with a one-off extent allocator. Free may block for memory to allocate space for an extent. Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas
* Now that we have UARTs running with fast interrupt handlers the atasam2009-06-232-35/+208
| | | | | | | | | | | | | driver's i/o ops must be locked to avoid chaos. Extend the cambria bus tag to support ata and add a spin lock. The ata driver is hacked to use that instead of it's builtin hack for ixp425. Once the ata driver is fixed to not be confused about byte order we can generalize the cambria bus tag code and make it generally useful. While here take advantage of our being ixp435-specific to remove delays when switching between byte+word accesses and to eliminate the 2us delay for the uarts (the spin lock overhead looks to do this for us).
* use consistent stylesam2009-06-231-1/+1
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* kill left over cruftsam2009-06-221-2/+0
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* enable optional GPS+RS485 uartssam2009-06-221-0/+14
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* o add a bus space tag that forces a 2usec delay between r/w ops; this issam2009-06-224-11/+120
| | | | | | | | | | used for the optional GPS+RS485 uarts on the Gateworks Cambria boards which otherwise are unreliable o setup the hack bus space tag for the GPS+RS485 uarts o program the gpio interrupts for the uarts to be edge-rising o force timing on the expansion bus for the uarts to be "slow" Thanks to Chris Lang of Gateworks for these tips.
* fix typosam2009-06-221-1/+1
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* o remove hack to write UUE+RTOIE in the uart's IER; force them with hintssam2009-06-223-21/+10
| | | | o honor hints for the rclk
* hook arm_post_filter to ACK GPIO interrupts; this fixes the interruptsam2009-06-221-0/+8
| | | | | | storm observed on the GPS+RS485 uarts on Gateworks Cambria boards Reviewed by: cognet
* always define Cambria GPS+RS485 mappings as they are no longer conditionalsam2009-06-221-4/+0
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* map the optional GPS and RS485 uart's on the Gateworks Cambria boardsam2009-06-222-21/+32
| | | | (may want to make these conditional)
* add ixp425_set_gpio to program the gpio interrupt typesam2009-06-223-10/+22
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* rewrite arm_get_next_irq to always make forward progress (should be optimized)sam2009-06-221-8/+20
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* kill stray whitespacesam2009-06-221-2/+2
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* move logic to ACK a GPIO to a separate functionsam2009-06-221-3/+9
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* swap order in ddb show gpio printfsam2009-06-221-2/+2
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* make type use consistentsam2009-06-221-1/+1
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* Disable write-back until I figure out what's wrong with it on the i81342.cognet2009-06-211-7/+1
| | | | There's no need to disable the MMU once we're done inflating the kernel.
* Track the kernel mapping of a physical page by a new entry in vm_pagethompsa2009-06-182-41/+163
| | | | | | | | | | | structure. When the page is shared, the kernel mapping becomes a special type of managed page to force the cache off the page mappings. This is needed to avoid stale entries on all ARM VIVT caches, and VIPT caches with cache color issue. Submitted by: Mark Tinguely Reviewed by: alc Tested by: Grzegorz Bernacki, thompsa
* enable npe-a now that it workssam2009-06-171-5/+5
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* Add workaround to get IXP435 NPE-A working: reseting NPE-A after NPE-Csam2009-06-171-28/+24
| | | | | | | | | | | causes both to become inoperative; this apparently was done by the original IAL code as a workaround for IMEM parity errors which we've not seen so just disable the reset. Note this problem does not occur on IXP425 boards. The linux driver does fuse-resets on each NPE but in the order NPE-A < NPE-B < NPE-C (when probing for which NPE's are present/operational); we may want to switch to a similar scheme but for now disable the resets until we see an issue.
* correct data/instruction memory sizes for non-ixp425 parts (thesesam2009-06-171-2/+8
| | | | are only used to bounds-check writes when loading firmware)
* remove IAL vestige for defining the max data/instruction memory size;sam2009-06-171-9/+2
| | | | | instead of defining them according to ixp46x add new defines so we can do this at run time
* o correct default miibase for NPE-B and NPE-C; these values aresam2009-06-171-7/+27
| | | | | | normally taken from the hints file so this should have no effect o set the port address "just in case" o add NPE-A support to the tx done qmgr callback
* add ixp4xx_write_feature_bitssam2009-06-172-0/+7
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* Move the memory layout definitions and logic from mvreg.h to mvwin.hmarcel2009-06-129-245/+287
| | | | | | | | so that it isn't exposured unless needed. In particular this means that it's easier to tune the memory layout based on board details. While here, remove inclusion of <machine/intr.h> from mvreg.h. This also contains exposure to SoC specifics in MI drivers, because NIRQ depends on the SoC.
* devclass_find_free_unit(xxx, 0) is identical to -1 for mostimp2009-06-121-1/+1
| | | | | applications (including this one). Switch to it since the former is a racy interface.
* strict kobj signatures: number of fixes for arm architectureavg2009-06-1110-19/+22
| | | | | | | no functional changes should result Reviewed by: imp, current@ Approved by: jhb (mentor)
* Eliminate devclass_find_free_unit call here, since -1 gives the sameimp2009-06-101-1/+1
| | | | net behavior.
* Pass the previously returned IRQ back to arm_get_next_irq() so thatmarcel2009-06-099-10/+10
| | | | | | | | | the implementation can guarantee forward progress in the event of a stuck interrupt or interrupt storm. This is especially critical for fast interrupt handlers, as they can cause a hard hang in that case. When first called, arm_get_next_irq() is passed -1. Obtained from: Juniper Networks, Inc.
* Disable interrupts to allow booting on firmware (e.g. U-Boot) thatmarcel2009-06-091-0/+5
| | | | | | has interrupts enabled and active. Obtained from: Juniper Networks, Inc.
* Invalidate cache in pmap_remove_all() on ARM.raj2009-06-081-0/+12
| | | | | | | | | | When pages are removed from virtual address space by calling pmap_remove_all() CPU caches were not invalidated, which led to read corruption when another page got mapped at this same virtual address at later time (the CPU was retrieving stale contents). Submitted by: Piotr Ziecik Obtained from: Semihalf
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