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* Back when I committed the arm port, I've been asked to movecognet2008-01-121-0/+69
* Add a missing \n.cognet2008-01-071-1/+1
* Add an access type parameter to pmap_enter(). It will be used to implementalc2008-01-031-2/+2
* Use correct function name in panic messageimp2008-01-031-1/+1
* Modernize comment about diagnostic.imp2008-01-031-2/+1
* Add configuration knobs for the superpage reservation system. Initially,alc2007-12-271-0/+7
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-251-1/+1
* - Fix a typo in comments.stas2007-12-231-1/+1
* Actually program the interrupt controller for priorities. As weimp2007-12-191-3/+43
* Use M_NOWAIT instead of M_WAITOK to cause malloc() to return NULLkevlo2007-12-171-1/+1
* - Don't return 0xffff if PHY id isn't equal 0. This allows PHYs withstas2007-12-161-2/+0
* There's no need to call pmap_vac_me_harder() in pmap_protect(), as itcognet2007-12-111-1/+0
* Add stubs to unbreak LINT.jkoshy2007-12-071-0/+4
* Fix style in previous commit.cognet2007-12-071-5/+6
* Erm, add a missing else, we do not want to increase the mapping counters forcognet2007-12-061-1/+1
* Break out stack(9) from ddb(4):rwatson2007-12-023-25/+119
* Fix a potential bug in pmap :cognet2007-12-021-5/+5
* Move the strongarm-specific files from conf/files.arm to sa11x0/files.sa11xO.cognet2007-12-021-0/+2
* Cleanup : make nexus standard, as it is mandatory anyway.cognet2007-12-0211-325/+0
* Close a race.cognet2007-12-022-19/+49
* Fixes for ARM9/ARM10 :cognet2007-11-281-1/+4
* Correct the logic : we can just invalidate the cache lines, and notcognet2007-11-281-1/+1
* In atomic_fetchadd_32(), do not blindly increase the value of %3.cognet2007-11-271-2/+3
* Remove the 'needbounce' variable from the _bus_dmamap_load_buffer()jhb2007-11-271-10/+4
* Prevent the leakage of wired pages in the following circumstances:alc2007-11-171-0/+21
* Add a kernel config file for the Hot-e HL200 (AT91RM92 based).cognet2007-11-171-0/+151
* o Rename cpu_thread_setup() to cpu_thread_alloc() to bettermarcel2007-11-141-2/+7
* generally we are interested in what thread did something asjulian2007-11-141-4/+4
* Add entries for the L2 cache-related functions for armv5.cognet2007-11-081-0/+5
* Fix for the panic("vm_thread_new: kstack allocation failed") andkib2007-11-057-7/+8
* Remove a staled comment, NPE-C should work fine.cognet2007-11-041-1/+0
* __CPU_XSCALE_PXA2XX -> CPU_XSCALE_PXA2X0kevlo2007-11-011-1/+1
* Don't define get_cachetype() for CPU_ARM9E unless it's going to be used.kevlo2007-10-311-1/+1
* kill commented out line of code.imp2007-10-291-1/+0
* Add an option to be able to override the value of the AT91 master clockcognet2007-10-251-0/+2
* Move some KB920x-specific options into the KB920x file.cognet2007-10-252-4/+4
* Oooops, get the end of the memory right.cognet2007-10-251-1/+1
* KERNBASE should really be KERNVIRTADDR there too.cognet2007-10-241-2/+2
* In ate_get_mac(), try to get the mac address in the right order, at leastcognet2007-10-241-6/+6
* Handle the case where PHYSADDR != KERNPHYSADDR (ie we do not load the kernelcognet2007-10-241-7/+11
* Correct a comment, this was not true anymore.cognet2007-10-241-2/+2
* correct guard variable names.imp2007-10-181-3/+3
* Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Notimp2007-10-187-22/+834
* Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (whichimp2007-10-181-2/+14
* Use the direct mapping, if available, for pmap_zero_page_xscale() as well.cognet2007-10-161-0/+15
* Do not use __XSCALE__ to detect if pld/strd/ldrd is available, usecognet2007-10-135-25/+25
* Define _ARM_ARCH_5E too, so that we know if pld/strd/ldrd are available.cognet2007-10-131-1/+6
* Spelling fix for interupt -> interruptkevlo2007-10-121-2/+2
* Make the PCI code aware of PCI domains (aka PCI segments) so we canmarius2007-09-303-2/+15
* Ok I hope I got it right this time.cognet2007-09-275-25692/+40
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