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* Remove COMPAT_43 from GENERIC (and other kernel configs). For amd64 there'snetchild2006-06-154-4/+0
| | | | | | | | | | | | | | | | | | | | | | an explicit comment that it's needed for the linuxolator. This is not the case anymore. For all other architectures there was only a "KEEP THIS". I'm (and other people too) running a COMPAT_43-less kernel since it's not necessary anymore for the linuxolator. Roman is running such a kernel for a for longer time. No problems so far. And I doubt other (newer than ia32 or alpha) architectures really depend on it. This may result in a small performance increase for some workloads. If the removal of COMPAT_43 results in a not working program, please recompile it and all dependencies and try again before reporting a problem. The only place where COMPAT_43 is needed (as in: does not compile without it) is in the (outdated/not usable since too old) svr4 code. Note: this does not remove the COMPAT_43TTY option. Nagging by: rdivacky
* Remove mpte optimization from pmap_enter_quick().ups2006-06-151-4/+2
| | | | | | | | | There is a race with the current locking scheme and removing it should have no measurable performance impact. This fixes page faults leading to panics in pmap_enter_quick_locked() on amd64/i386. Reviewed by: alc,jhb,peter,ps
* MFp4:cognet2006-06-122-10/+139
| | | | | | | - Try hard to calculate a safe sp, so that the stack doesn't get smashed while uncompressing or relocating the kernel. - Bring in code needed to calculate the cacheline size etc, needed for arm9_idcache_wbinv_all.
* MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to becognet2006-06-121-1/+1
| | | | able to boot fat kernels.
* Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match thealc2006-06-111-6/+2
| | | | | | current interface with the machine-independent layer. Without this change, the page daemon would only have been awakened the first time that the number of pv entries went above the high water mark, not each time.
* Eliminate spl calls.alc2006-06-111-11/+0
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* Add a lock assertion. Remove dead (locking) code. Change some whitealc2006-06-101-36/+4
| | | | | | space. Reviewed by: cognet@
* Add pmap locking to pmap_extract().alc2006-06-091-4/+8
| | | | Tested by: cognet@
* Oops it seems I forgot to remove ARM32_NEW_VM_LAYOUT from here.cognet2006-06-073-3/+0
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* Add pmap locking to pmap_fault_fixup().alc2006-06-071-16/+7
| | | | | | Add an assertion to pmap_vac_me_harder(). Tested by: cognet@
* Properly synchronize access to the pmap in pmap_extract_and_hold().alc2006-06-071-3/+2
| | | | | | Eliminate an unneeded variable from pmap_extract_and_hold(). Tested by: cognet@
* Now that we use pmap_mapdev_boostrap(), we can get ride of the got_mmucognet2006-06-073-31/+3
| | | | | | hack. Submitted by: kevlo
* Remove sa1_cache_clean_addr. It isn't needed.imp2006-06-071-2/+0
| | | | Submitted by: kevlo
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-062-64/+15
| | | | completely nuke the !ARM32_NEW_VM_LAYOUT case.
* Remove a bogus, useless, "i++".cognet2006-06-061-1/+0
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* Add partial pmap locking.alc2006-06-061-30/+34
| | | | Tested by: cognet@
* Add partial pmap locking.alc2006-06-062-8/+29
| | | | | | Eliminate the unused allpmaps list. Tested by: cognet@
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-2/+2
| | | | | | as an option. Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
* vm_page_alloc_contig() can sleep, so don't even think about using itcognet2006-06-051-8/+9
| | | | in the M_NOWAIT case.
* Introduce the function pmap_enter_object(). It maps a sequence of residentalc2006-06-051-1/+28
| | | | | | | pages from the same object. Use it in vm_map_pmap_enter() to reduce the locking overhead of premapping objects. Reviewed by: tegge@
* Don't #error if no CPU is defined but we're not compiling the kernel.cognet2006-06-021-2/+2
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* Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.cognet2006-06-011-1/+1
| | | | | | This has been committed by mistake. Reported by: ssouhlal
* Introduce pmap_enter_locked() and use it to reimplement pmap_enter_quick().alc2006-06-011-11/+19
| | | | Tested by: cognet@
* Avoid a LOR by unlocking the vm_page_queue_mtx before calling uma_zalloc,cognet2006-05-311-5/+35
| | | | and freeing the allocated memory if another thread already did the same.
* If our buffer is not aligned on the cache line size, write back/invalidatecognet2006-05-311-7/+10
| | | | | | the first and last cache line in PREREAD, and just invalidate the cache lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which could lead to stale data overriding what has been transfered by DMA.
* Ooops arm10 is armv5, not armv4.cognet2006-05-311-3/+3
| | | | Submitted by: kevlo
* Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,cognet2006-05-311-1/+1
| | | | to appease -Wundef.
* Protect the mapping used for pmap_copy_page/pmap_zero_page with acognet2006-05-301-2/+15
| | | | mutex.
* To avoid problems, invalidate the data cache and disable the MMU oncecognet2006-05-301-2/+32
| | | | we're done uncompressing the kernel.
* In pmap_is_prefaultable(), assert that the pte isn't NULL ifcognet2006-05-301-0/+1
| | | | | | pmap_get_pde_pte() returns TRUE. Suggested by: ssouhlal
* The Assabet has 32MB of RAM, not 16.cognet2006-05-301-2/+3
| | | | Submitted by: kevlo
* In pmap_mapdev we correctly round the address off to the nearest pagebenno2006-05-301-1/+1
| | | | boundary, but we must also add the offset back on to the va we return.
* Uncomment the call to cpu_idcache_wbinv_all() after the MMU has beencognet2006-05-301-1/+1
| | | | | | | | | | enabled. It has been commented out for a reason I forgot but I suspect does not apply anymore. Technically speaking it's not required to do it, has the data and the instruction cache have been disabled in _start(). However, it may change in the future, so I don't want to rely on this behavior. Submitted by: kevlo
* Nuke sa11x0_attach_args. It's a NetBSDIsm, and we have no use for it.cognet2006-05-291-9/+0
| | | | Submitted by: kevlo
* Remove any reference to enable_mmu(), it's been gone for a long time.cognet2006-05-262-2/+0
| | | | Submitted by: kevlo
* Use pmap_devmap_bootstrap(), instead of mapping the SACOM1 registerscognet2006-05-234-6/+42
| | | | | | | with pmap_map_entry. More use of macros instead of hardcoding the addr. Submitted by: kevlo
* Use macros instead of hardcoding the address for SACOM1. Also don'tcognet2006-05-223-4/+7
| | | | | | pretend we're working with SACOM3, as we're really mapping SACOM1. Submitted by: kevlo
* We have an implementation of generic_bs_rr_1, so use it, as some drivers usecognet2006-05-192-2/+2
| | | | | | it. Submitted by: kevlo
* Comment out SYSCTL_OMIT_DESCR until it's committed.cognet2006-05-191-1/+1
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* Implement sa11x0_bs_unmap.cognet2006-05-181-3/+15
| | | | Submitted by: kevlo
* Make this compile (UART_IPEND_* => SER_INT_*).cognet2006-05-181-2/+2
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* Add definitions for atomic_subtract_rel_32, atomic_add_rel_32 andcognet2006-05-151-0/+3
| | | | atomic_load_acq_32, needed for hwpmc.
* Display real/avail memory as per other platforms.benno2006-05-151-3/+29
| | | | Approved by: cognet
* Switch to a 64bit time_t, while it's not a big problem to do so.cognet2006-05-151-1/+1
| | | | Suggested by: imp
* Resurrect Skyeye support :cognet2006-05-138-29/+53
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* Tidy up a bit...imp2006-05-131-12/+0
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* Clean out sysctl machdep.* related defines.phk2006-05-111-8/+0
| | | | The cmos clock related stuff should really be in MI code.
* Get this to compile :cognet2006-05-112-1/+48
| | | | | | - The prototype of uart_bus_probe() hasn't been changed in cvs yet, so use the old one. - Add at91_pdcreg.h, needed by uart_dev_at91usart.c.
* Move the call to cpu_setup() before the call to vm_ksubmap_init().cognet2006-05-101-1/+1
| | | | | | | | | vm_ksubmap_init() calls pmap_copy_page(), which uses the mini data cache to do the copy, but we're running uncaching before cpu_setup(). For some reason it hasn't been a problem so far, but it is for the PXA255. Spotted out by: benno
* Setting the rid of the resource is a good idea, but we still need to returncognet2006-05-051-0/+1
| | | | the resource after.
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