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* Remove COMPAT_43 from GENERIC (and other kernel configs). For amd64 there'snetchild2006-06-154-4/+0
* Remove mpte optimization from pmap_enter_quick().ups2006-06-151-4/+2
* MFp4:cognet2006-06-122-10/+139
* MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to becognet2006-06-121-1/+1
* Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match thealc2006-06-111-6/+2
* Eliminate spl calls.alc2006-06-111-11/+0
* Add a lock assertion. Remove dead (locking) code. Change some whitealc2006-06-101-36/+4
* Add pmap locking to pmap_extract().alc2006-06-091-4/+8
* Oops it seems I forgot to remove ARM32_NEW_VM_LAYOUT from here.cognet2006-06-073-3/+0
* Add pmap locking to pmap_fault_fixup().alc2006-06-071-16/+7
* Properly synchronize access to the pmap in pmap_extract_and_hold().alc2006-06-071-3/+2
* Now that we use pmap_mapdev_boostrap(), we can get ride of the got_mmucognet2006-06-073-31/+3
* Remove sa1_cache_clean_addr. It isn't needed.imp2006-06-071-2/+0
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-062-64/+15
* Remove a bogus, useless, "i++".cognet2006-06-061-1/+0
* Add partial pmap locking.alc2006-06-061-30/+34
* Add partial pmap locking.alc2006-06-062-8/+29
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-2/+2
* vm_page_alloc_contig() can sleep, so don't even think about using itcognet2006-06-051-8/+9
* Introduce the function pmap_enter_object(). It maps a sequence of residentalc2006-06-051-1/+28
* Don't #error if no CPU is defined but we're not compiling the kernel.cognet2006-06-021-2/+2
* Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.cognet2006-06-011-1/+1
* Introduce pmap_enter_locked() and use it to reimplement pmap_enter_quick().alc2006-06-011-11/+19
* Avoid a LOR by unlocking the vm_page_queue_mtx before calling uma_zalloc,cognet2006-05-311-5/+35
* If our buffer is not aligned on the cache line size, write back/invalidatecognet2006-05-311-7/+10
* Ooops arm10 is armv5, not armv4.cognet2006-05-311-3/+3
* Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,cognet2006-05-311-1/+1
* Protect the mapping used for pmap_copy_page/pmap_zero_page with acognet2006-05-301-2/+15
* To avoid problems, invalidate the data cache and disable the MMU oncecognet2006-05-301-2/+32
* In pmap_is_prefaultable(), assert that the pte isn't NULL ifcognet2006-05-301-0/+1
* The Assabet has 32MB of RAM, not 16.cognet2006-05-301-2/+3
* In pmap_mapdev we correctly round the address off to the nearest pagebenno2006-05-301-1/+1
* Uncomment the call to cpu_idcache_wbinv_all() after the MMU has beencognet2006-05-301-1/+1
* Nuke sa11x0_attach_args. It's a NetBSDIsm, and we have no use for it.cognet2006-05-291-9/+0
* Remove any reference to enable_mmu(), it's been gone for a long time.cognet2006-05-262-2/+0
* Use pmap_devmap_bootstrap(), instead of mapping the SACOM1 registerscognet2006-05-234-6/+42
* Use macros instead of hardcoding the address for SACOM1. Also don'tcognet2006-05-223-4/+7
* We have an implementation of generic_bs_rr_1, so use it, as some drivers usecognet2006-05-192-2/+2
* Comment out SYSCTL_OMIT_DESCR until it's committed.cognet2006-05-191-1/+1
* Implement sa11x0_bs_unmap.cognet2006-05-181-3/+15
* Make this compile (UART_IPEND_* => SER_INT_*).cognet2006-05-181-2/+2
* Add definitions for atomic_subtract_rel_32, atomic_add_rel_32 andcognet2006-05-151-0/+3
* Display real/avail memory as per other platforms.benno2006-05-151-3/+29
* Switch to a 64bit time_t, while it's not a big problem to do so.cognet2006-05-151-1/+1
* Resurrect Skyeye support :cognet2006-05-138-29/+53
* Tidy up a bit...imp2006-05-131-12/+0
* Clean out sysctl machdep.* related defines.phk2006-05-111-8/+0
* Get this to compile :cognet2006-05-112-1/+48
* Move the call to cpu_setup() before the call to vm_ksubmap_init().cognet2006-05-101-1/+1
* Setting the rid of the resource is a good idea, but we still need to returncognet2006-05-051-0/+1
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