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* MFC 266621: Eliminte spurious interrupts caused by ARM weak memory ordering.ian2014-05-274-2/+76
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* MFC r264096, r264097, r264099 r264100, r264101, r264102, r264119:ian2014-05-273-18/+63
| | | | | | Fixes to the ti_sdhci and sdhci drivers (fix clock divisor calcs). Use the ti_sdhci driver instead of ti_mmchs for Pandaboard.
* MFC 258287: Implement pmap_align_superpage().ian2014-05-181-0/+14
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* MFC 257231:ian2014-05-181-1/+5
| | | | | Make sure the PCB is aligned on 8 bytes, we may use ldrd/strd to access it, which may have strong alignment requirements.
* MFC 257189:ian2014-05-181-1/+1
| | | | | Fix an itt instruction. We need to execute both the mov and b instructions when building for Thumb.
* MFC 256942, 256943:ian2014-05-182-4/+9
| | | | | | | | - Fix a typo. - Use bus_dmamap_unload(), it is not optional. - The new allocator won't return coherent memory for any size > PAGE_SIZE, so don't assume we have coherent memory, and explicitely use bus_dmamap_sync().
* MFC 256873: Make watchdog function conform watchdog(9):ian2014-05-181-0/+12
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* MFC 256941: make sure the frame is indeed in the kernel memory.ian2014-05-181-1/+4
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* MFC 265624, 265739: Fix interrupt parent property in dts, add SMP support.ian2014-05-184-0/+195
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* MFC 265913, 265914:ian2014-05-181-10/+6
| | | | | | | | Interrupts need to be disabled on entry to cpu_sleep() for ARM. Given that and the need to be in a critical section when switching to idleclock mode for event timers, use spinlock_enter()/exit() to achieve both needs. Clean up some style nits.
* MFC 265861, 265870:ian2014-05-185-4/+42
| | | | | | | Make the hardware memory and instruction barrier functions work on armv4 and armv5 as well. Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
* MFC 265852: Map device memory using PTE_DEVICE rather than PTE_NOCACHE.ian2014-05-1812-55/+55
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* MFC 265694, 265705, 265784:ian2014-05-184-70/+78
| | | | | | | | | | | Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of the common locore.S file and into the mv/armadaxp directory. Consolidate all the AP core startup stuff under a single #ifdef SMP block Call idcache_inv_all from the AP core entry code before turning on the MMU. Also, enable instruction and branch caches, which should be safe now that they're properly initialized/invalidated first.
* MFC 265440, 265441, 265444, 265445, 265446, 265447:ian2014-05-183-44/+117
| | | | | | | | | | | | | | | | | | Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor style(9) nits. Use DEVMETHOD_END. Break out the code that figures out the L2 cache geometry to its own routine, so that it can be called from multiple places in upcoming changes. Call platform_pl310_init() before enabling the controller, and handle the case where the controller is already enabled. Add defines for the bits in the PL310 debug control register. Add a public routine to set the L2 cache ram latencies. This can be called by platform init routines to fine-tune cache performance. Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
* MFC 265155, 265254:ian2014-05-1819-4/+42
| | | | | | Omit from the universe build all config files tagged with #NO_UNIVERSE. Add FDT to the VYBRID kernel.
* MFC 265207: Use arm_devmap_add_entry() to setup static device mapping.ian2014-05-171-19/+3
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* MFC 265156: Remove WANDBOARD.common, it was replaced by IMX6.ian2014-05-171-159/+0
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* MFC 265099, 265148, 265690:ian2014-05-177-50/+139
| | | | | | | | | Add SMP support for Zedboard. Use edge-triggered interrupts rather than polling loops to avoid missing transitions of the INIT_B line. Also, release the mutex during uiomove(). Convert the Zynq SoC support to the new routines for static device mapping.
* MFC 265111: Make a declaration into a proper function prototype.ian2014-05-171-1/+1
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* MFC 265035: Move duplicated code to print l2 config into the common code.ian2014-05-174-68/+45
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* MFC 265023, 265024, 265036:ian2014-05-174-3/+28
| | | | | | | | | | There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so map them both to the same interrupt number like other arches do. Flush and invalidate caches on each CPU as part of handling IPI_STOP. Don't use multiprocessing-extensions instruction on processors that don't support SMP.
* MFC 264990, 264994, 265020, 265025:ian2014-05-176-8/+30
| | | | | | | | | | | | | | | | Call cpu_icache_sync_range() rather than sync_all since we know the range and flushing the entire icache is needlessly expensive. Provide a proper armv7 implementation of icache_sync_all rather than using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the operation to other cores. In elf_cpu_load_file() use icache_sync_all() and explain why it's needed (and why other sync operations aren't). Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed. Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache flush. (Either it was missing here, or it isn't needed in the minidump case. Adding it here seems like the safer path to consistancy.)
* MFC 264977:ian2014-05-178-46/+117
| | | | | | Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead define a few imx_ccm_foo() functions that are implemented by the imx51 or imx6 ccm code.
* MFC 264702: Remove uncessary armv6 cache and TLB maintenance ops.ian2014-05-171-10/+0
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* MFC 264251: Updates to i.MX53:ian2014-05-175-67/+114
| | | | | * Define support for the SDHCI driver, although it doesn't work yet * Fix the memory mappings for IPU
* MFC 264219: Move sys/arm/econa to sys/arm/cavium/cns11xx.ian2014-05-1718-25/+25
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* MFC 264203, 264204, 264206, 264218:ian2014-05-171-2/+2
| | | | | | | | Tell VM we now have ARM platforms with physically discontiguous memory. Define the full 1024M of ram on the imx51 and imx53 boards. Use a more professional uart device description.
* MFC 264180, 264181, 264182:ian2014-05-171-0/+2
| | | | | | | | Follow files.imx51 and add vt support for imx53. Add fsl,imx53 compatible string. Need to include machine/fdt.h in vt_early_fb.c
* MFC 264160: Remove code under PMAP_CACHE_VIVT, not compiled on armv6.ian2014-05-173-15/+0
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* MFC 264150: Exynos: Correct the end address of the video frame buffer.ian2014-05-171-3/+5
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* MFC 264183: Add a couple more required TLB flushes.ian2014-05-171-1/+6
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* MFC 264137: Switch wandboards over to the common IMX6 kernel config, whichian2014-05-171-0/+1
| | | | has SMP enabled. Also switch IMX6 to use SCHED_ULE.
* MFC 264137: Switch wandboards over to the common IMX6 kernel config, whichian2014-05-174-6/+6
| | | | has SMP enabled. Also switch IMX6 to use SCHED_ULE.
* MFC 264128, 264129, 264130, 264135,ian2014-05-173-100/+134
| | | | | | | | | | | | | | | | | | | Fix TTB set operation for armv7. Perform sychronization (by "isb" barrier) after TTB is set. Fix TLB maintenance issues for armv6 and armv7. - Add cpu_cpwait to comply with the convention. - Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove with distinguishing between D and ID pages. - Modify pmap init/bootstrap invalidations to ID, just to be safe. - Fix TLB-inv and PTE_SYNC ordering. Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page(). This is performance enhancement rather than bugfix. We don't support any ARM systems with an ISA bus and don't need a freelist of memory to support ISA addressing limitations.
* MFC 264052, 264057, 264065, 264094, 264103, 264120ian2014-05-175-80/+217
| | | | | | | | | | | | | | | | | Actually save the mpcore clock frequency retrieved from fdt data. imx6.. - Don't call sdhci_init_slot() until after handling the FDT properties related to detecting card presence. - Flag several sysctl variables as tunables. - Rework the cpu frequency management code for imx6 to add "operating points" and min/max frequency controls. generic timer... - Setup both secure and non-secure timer IRQs. We don't know our ARM security state, so one of them will operate. - Don't set frequency, since it's unpossible in non-secure state. Only rely on DTS clock-frequency value or get clock from timer.
* MFC 264054, 264056ian2014-05-173-0/+7
| | | | | | | | Switch imx6 to using the mpcore per-cpu event timers, but continue to use the GPT timer, which is fixed-frequency, as a timecounter. Change NO_EVENTTIMERS from an arm-specific to an MI option, so that it can be used in MI code.
* MFC 264019, 264041, 264048, 264049, 264050, 264051ian2014-05-173-36/+133
| | | | | | | | | | | | | | Add support for event timers whose clock frequency can change while running. Apparently all ARM configs build kern_et.c, but only a few of them also build kern_clocksource.c, un-break the build by not referencing functions in kern_clocksource if NO_EVENTTIMERS is defined. Add variable-frequency support to the arm mpcore eventtimer driver. mpcore_timer: Disable the timer and clear any pending bit, then setup the new counter register values, then restart the timer. Also re-nest the parens properly for casting the result of converting time and frequency to a count.
* MFC 263910, 263913, 263914, 263933, 263934, 263935, 263936, 263981, 263982,ian2014-05-1724-281/+3039
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add more flags for the fpexc register from the ARM1176JZF-S Manual Initialise fpscr to a sane value when we create the pcb. This sets NaNs to be the default NaN and for denormalised numbers to be flushed to zero. VFP fixes/cleanups for ARM11: * Save the required VFP registers on context switch. If the exception bit is set we need to save and restore the FPINST register, and if the fp2v bit is also set we need to save and restore FPINST2. * Move saving and restoring the floating point control registers to C. * Clear the fpexc exception and fp2v flags on a floating-point exception. * Signal a SIGFPE if the fpexc exception flag is set on an undefined instruction. This is how the ARM core signals to software there is a floating-point exception. Add Cortex-A15 cpu id revisions. Exynos/Arndale... - Merge SoC-common parts - Enable iicbus device - Directly call kmem_alloc_contig to allocate framebuffer memory and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer). This fixes screen refreshing problem when data is updated too slowly. - Add support for keyboard used in Samsung Chromebook (ARM machine) Support covers device drivers for: - Interrupt Combiner - gpio/pad, External Interrupts Controller (pad) - I2C Interface - Chrome Embedded Controller - Chrome Keyboard - Use new gpio dev class in EHCI driver - Expand device tree information - Release i2c bus on detach.
* Adds the ADC driver for TI AM3xxx SoC family.loos2014-05-177-0/+793
| | | | | | | | | | | | | | | The ADC has a 12bit resolution and its raw output can be read via sysctl(8) interface. The driver allows the setup of ADC clock, samples average and open delay (the number of clock cycles to wait before start the conversion). The TSC_ADC module is set in the general purpose mode (no touchscreen support). Tested on Beaglebone-black. Written based on AM335x TRM.
* MFC 263631, 263637, 263664, 263676, 263679, 263698, 263711,ian2014-05-1730-75/+242
| | | | | | | | | | | | | | | | | | Implement __flt_rounds for ARMv6 hard-float. The fpscr register stores the current rounding mode used by the VFP unit. Simplify how we build MACHINE_ARCH. There are 3 options that may be set however only arm, armeb, armv6, and soon armv6hf will be used. Add the llvm/clang patch for r263619. Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are identical this allows us to build for both v6 and v7 together. Add code for enabling second CPU core for A20 SoC. Enable SMP on Cubieboard2. Switch to freebsd.org emal address in copyright.
* MFC 263250, 263251, 263424, 263425, 263426, 263427, 263430, 263431ian2014-05-179-20/+618
| | | | | | | | | | | | | | | | | Use the same cache terminology as the ARM docs in comments. No functional changes. Use armv7 TLB flush code, not arm11, for cortex-a processors. Exynos/ Arndale... - Disable debugging by default. - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add display-related and clk devices to the tree - Prevent resources intersection with EHCI driver - Add driver for Display Controller. - Add support for Samsung Chromebook (ARM Cortex A15 machine). - Rename mct and ehci drivers files to match common naming.
* MFC 263301ian2014-05-1749-160/+160
| | | | | | In kernel config files, it is supposed to be 'options<space><tab>' not 'options<tab><tab>', per long standing (but recently not so strictly enforced) convention.
* MFC 263245: Make all the comments '# ' and align to same column.ian2014-05-1746-1735/+1734
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* MFC 263199, 263207ian2014-05-171-0/+3
| | | | | | Fix error mesasge in dtc. Add tmpfs, mbr, and bsdlabel options back to wandboard kernel config.
* MFC 263036, 263059: delete advertising clause in licenses, renumber.ian2014-05-172-10/+2
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* MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,ian2014-05-1782-6069/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
* MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,ian2014-05-1788-445/+516
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949, 262950 Strip arm/conf/DEFAULTS down to just items that are mandatory for running the architecture. Move all the files named foo/common.c to foo/foo_common.c Initial cut for DTS on the hl201 board. Add commented out dts for sam9260ek as well as early printf support. Make clock optional on uart nodes, then back it out ("I don't know what I was thinking, but it is lame.") Set the baud rate if it isn't 0 Make at91_soc_id() public. Properly round at91 resource on unmapping. Move AT91 AIC related stuff to own file. Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32. Follow r262916 with one more config file that references a renamed common.c Remove bogus AT91 define that causes compile errors. Most of the defines for SAM9X are going away soonish anyway (once FDT works), but until then... Remove all dregs of a per-thread undefined-exception-mode stack. Rework the VFP code that handles demand-based save and restore of state. Always call vfp_discard() on thread death. When a thread begins life it doesn't own the VFP hardware state on any cpu. Make undefined exception entry MP-safe.
* MFC 258211, 257775, 258096,ian2014-05-165-290/+12
| | | | | | Add mbox and pruss drivers to ti build. Use common bus_space-v6 instead of local copies.
* MFC 262695, 262708, 262709, 262710, 262711, 262728, 262870, 262877, 262880,ian2014-05-1633-69/+2086
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262885, 262891, 262903, imx6: Add a tunable to set the number of active cores, enable SMP by default. ffec: Fix multicast filtering. Allwinner a10/a20... - Add gpio and clock bits for A10/A20's EMAC ethernet controller driver - EMAC gpio configuration - EMAC clock activation - Add Static Random Access Memory controller driver for A10/A20. A10/A20's SRAM is used by devices, such as CPU, EMAC, for extra fast memory or as cache. - Add EMAC 10/100 Ethernet controller driver for A10/A20. It is available mostly in A10 devices like Hackberry, Marsboard, Mele A1000, A2000, A100 HTPC, cubieboard1 and A20 device like cubieboard2. TX performance can be improved using both channels 0 and 1. RX performance is poor and needs improvement with the assistance of external DMA controller in case there - Add EMAC and SRAM controller entries to FDT. - Add EMAC device to kernel config files and enable EMAC, SRAM drivers. OMAP: When calculating the MPU freq, make sure not to overflow. Vybrid: - Add driver for Port control and interrupts (PORT). - Export panel info to DTS - Reset all the layers before setup first one - Enable display nandfs: Slight code reordering to make error branch last. Add option TMPFS to arm/conf/DEFAULTS, remove it from the few configs that have it individually. Concensus on freebsd-arm@ is that it should be included in all ARM kernels. Fix the arm sys_sigreturn(): its argument is a struct ucontext, not a struct sigframe containing the struct ucontext.
* MFC r262591, r262592, r262593, r262597, r262598, r262599, r262600, r262601,ian2014-05-163-0/+315
| | | | | | | | | | | | | | | | | | r262606 Initial import of Linux/Vendor DTS files for various embedded boards. Initial import of DTS files from Linux Correct initial import script New AT91 devices or fdt probe added to existing devices. Some of these are just stubs for testing the new dts. - nand - SDRAMC - shdwc - tcb - usb host and gadget
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