| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | MFC r304285: | kib | 2016-09-16 | 3 | -16/+2 |
* | MFC 305771, 305772: | andrew | 2016-09-13 | 3 | -1/+5 |
* | MFC 305767: | andrew | 2016-09-13 | 1 | -0/+22 |
* | MFC 303299, 303475: | andrew | 2016-09-07 | 1 | -0/+2 |
* | MFC 303592: | andrew | 2016-09-07 | 1 | -9/+15 |
* | MFC 303585, 303587: | andrew | 2016-09-07 | 1 | -8/+7 |
* | MFC 303594, 303610: | andrew | 2016-09-07 | 1 | -0/+47 |
* | MFC 304625: | andrew | 2016-09-07 | 1 | -2/+2 |
* | MFC 303307, 303308, 303309 clean up the arm64 MP code: | andrew | 2016-09-07 | 1 | -12/+9 |
* | MFC 303661: | andrew | 2016-09-07 | 1 | -13/+13 |
* | MFC 304140: | andrew | 2016-09-07 | 2 | -3/+150 |
* | MFC 302849, 302851, 302896 GICv3 improvements: | andrew | 2016-09-07 | 4 | -110/+101 |
* | MFC 302847, 302848, 302852, 302853: | andrew | 2016-08-31 | 8 | -588/+1 |
* | MFC 302789: | andrew | 2016-08-31 | 2 | -1/+17 |
* | MFC r303923: | ed | 2016-08-15 | 1 | -0/+2 |
* | MFC r302448: | ed | 2016-07-12 | 1 | -0/+1 |
* | Remove the old pre-INTRNG arm64 interrupt framework. GENERIC was switched | andrew | 2016-07-06 | 6 | -3554/+0 |
* | ARM64: fix DMAP calculation | wma | 2016-06-30 | 1 | -2/+2 |
* | Fix a race when the hardware has raised an exception with an unknown or | andrew | 2016-06-22 | 1 | -4/+3 |
* | Update comments for the MD functions managing contexts for new | kib | 2016-06-16 | 2 | -12/+11 |
* | Switch arm64 to use intrng by default. The old interrupt handling code can | andrew | 2016-06-07 | 2 | -15/+1 |
* | INTRNG - change the way how an interrupt mapping data are provided | skra | 2016-06-05 | 2 | -1/+5 |
* | Add the GICv3 ITS intrng driver. As the interface to the interrupt | andrew | 2016-06-03 | 5 | -10/+1706 |
* | Return real error value instead of hard-coded ENXIO (fix after r300149) | zbb | 2016-06-01 | 1 | -1/+3 |
* | dpcpu_init should have also passed in the calculated cpuid, not the | andrew | 2016-05-31 | 1 | -1/+1 |
* | Allow the kernel to boot on a CPU where the devicetree has numbered it with | andrew | 2016-05-31 | 1 | -12/+47 |
* | Enable setting BF_COHERENT on DMA tags. This allows the kernel to start | andrew | 2016-05-31 | 1 | -2/+0 |
* | Mark the ThunderX and generic PCI drivers as cache-coherent when we know | andrew | 2016-05-31 | 3 | -0/+29 |
* | Extract the correct bits from the GICD_TYPER register. The interrupt count | andrew | 2016-05-20 | 1 | -1/+1 |
* | Add more useful GICv3 register definitions. While here fix | andrew | 2016-05-20 | 1 | -1/+25 |
* | Filter out BUS_DMASYNC_POSTWRITE sync operations, there is nothing for us | andrew | 2016-05-20 | 1 | -0/+3 |
* | Enable NEW_PCIB on arm64. | andrew | 2016-05-20 | 1 | -0/+1 |
* | Handle PCI_RES_BUS on the generic and ThunderX PCIe drivers. This has been | andrew | 2016-05-20 | 1 | -0/+14 |
* | Define PCI_RES_BUS for NEW_PCIB | andrew | 2016-05-19 | 1 | -0/+3 |
* | Return the struct intr_pic pointer from intr_pic_register. This will be | andrew | 2016-05-18 | 1 | -2/+2 |
* | Add support for MSI/MSIX deallocation on GICv3-ITS | zbb | 2016-05-18 | 2 | -8/+87 |
* | The GIC (v2 at least) has a bit in the TYPER register to indicate whether the... | bz | 2016-05-17 | 2 | -4/+10 |
* | Add an arm64 kernel config to help testing intrng. It is expected this | andrew | 2016-05-17 | 1 | -0/+15 |
* | Clean up the GICv3 intrng code: | andrew | 2016-05-17 | 1 | -4/+10 |
* | Add intrng support to the GICv3 driver. It lacks ITS support so won't handle | andrew | 2016-05-16 | 3 | -4/+626 |
* | Move the call to intr_pic_init_secondary to the same place as in the | andrew | 2016-05-16 | 1 | -5/+3 |
* | Add support for intrng to arm64. As the GICv3 drivers will need to be | andrew | 2016-05-16 | 4 | -1/+298 |
* | Teach the ThunderX PCI PEM driver about intrng. This will be used later | andrew | 2016-05-16 | 1 | -0/+55 |
* | Add a pcib interface for use by interrupt controllers that need to | andrew | 2016-05-16 | 5 | -61/+97 |
* | Add support to the arm64 busdma to handle the cache. For now this is | andrew | 2016-05-13 | 2 | -23/+203 |
* | Rename the internal BUC_DMA_* flags to BF_* so they won't conflict with | andrew | 2016-05-12 | 1 | -20/+20 |
* | Restrict the memory barriers in bus_dmamap_sync to just the operations | andrew | 2016-05-12 | 1 | -46/+47 |
* | Call busdma_swi from swi_vm as is done from other architectures. | andrew | 2016-05-11 | 2 | -1/+4 |
* | On arm64 always create a bus_dmamap_t object. This will be use to hold the | andrew | 2016-05-11 | 1 | -44/+72 |
* | Add data barriers to the arm64 bus_dmamap_sync function. We need these | andrew | 2016-05-11 | 1 | -1/+14 |